The course are taught in English. The subject is offered in the study tracks of Electronic Engineering Master where the technological knowledge of the integration processes is need, the subject is also compulsary in the study plan for Nanotechnologie for ICTs Master. The subject is offered during the first semester of the second year and is focused on the technological aspects of system integration with attention to micro and nano technologies currently available to the designers.

-Classification of the most relevant CMOS fabrication processes in accordance to ITRS roadmap and their evaluation in terms of figures of merit (Ion, Ioff, intrinsic time....) -Evaluation of consequences due to the scaling techniques used in integration processes both on the single devices and on the inteconnects among structures. -Knowledge of the main fabrication technologies for nanometer scale devices: advanced gate and channel technologies. -Knowledge of adavanced CMOS processes as SOI, Double gate, FinFET, GAA. -Knowlege of the inteconnections and packaging technologies and evaluation of their electrical behavior in term of delays, crosstlak, IR drop. -Ability of using simulation tools for the estimation of the consequences on device and system of the technological parameters. -Knowledge of the emerging technologies that can be considered a possible replacement of CMOS processes.

Good Knowledge of the basic technological processes used in planar technology as photolitography, doping, epitaxy, oxidation and film deposition. Deep knowledge of MOS systems and MOSFET devices: main equations for long and short channel devices with great care to the the conduction in velocity saturation and in subthreshold conditions. Electrical modelling of the intercconects in the integrated circuits.

-Classification of the most used CMOS fabrication processes (HP High performance,LOP Low Operating Power, LSTP Low Stand By Power) -Technological scaling: analysis of the consequences at device level, at interconnects level and at system level. -Advanced CMOS processes: gate structures. -Advanced CMOS processes: channel and source drain structures. -FinFET and GAA technology. -Evaluation of the technological choices on the system level performance: frequency, dynamic power, static power. -Interconnects techniques: damascene, dual damascene, planarization and low-k dielectrics. -Packaging technologies. -Emerging technologies: fabrication of nano wires. -Emerging Tecnologies: 3D integration.

The practises will be focused on the evaluation of the main system parameters as function of the technological choices adopted during the system integration: in more details by mean of some cases of study will be studied a methodology to evaluate the system behavior from the device and inteconnects parameters both for CMOS processes and for 'emerging' technologies. Some laboratories based on MASTAR simulator will be assigned: starting from a standard process the student will modify its technological parameters to satisfy system level constraints. During the second part of the semester a mandatory project is assigned. The project will be developed by groups of students with the main aim of developimg a tool for the system level prediction.

The main manual book used is the ITRS roadmap in web published version on http://www.itrs2.net. The most used sections are: Process Integration Devices and Structures; Interconnects; Assembly; Emerging Research Devices. Slides of lecture and some related scientific papers for insights are available on web pages of the subject.

Modalità di esame: Prova orale obbligatoria; Prova scritta tramite PC con l'utilizzo della piattaforma di ateneo;

The exam is organized: 1)a brief (40 minutes) closed book written section where 11 multiple choice questions will enable the student to go on the exam if at least 7/11 answers will be right; this section does not contribute to the final score; 2)a 30 minutes oral exam on the whole subjects (classes and practises) with the weight of 0.6 on the final score will be evaluated in /30; 3)a project work (assigned during the semester) will be presented and evaluated in /30 with a weight of 0.4.

Modalità di esame: Prova scritta (in aula); Prova orale obbligatoria; Prova scritta tramite PC con l'utilizzo della piattaforma di ateneo;

The exam is organized: 1)a brief (40 minutes) closed book written section where 11 multiple choice questions will enable the student to go on the exam if at least 7/11 answers will be right; this section does not contribute to the final score; 2)a 30 minutes oral exam on the whole subjects (classes and practises) with the weight of 0.6 on the final score will be evaluated in /30; 3)a project work (assigned during the semester) will be presented and evaluated in /30 with a weight of 0.4.