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Integrated systems technology

01NOMOQ

A.A. 2023/24

Course Language

Inglese

Degree programme(s)

Master of science-level of the Bologna process in Ingegneria Elettronica (Electronic Engineering) - Torino

Course structure
Teaching Hours
Lezioni 42
Esercitazioni in aula 12
Esercitazioni in laboratorio 6
Lecturers
Teacher Status SSD h.Les h.Ex h.Lab h.Tut Years teaching
Piccinini Gianluca Professore Ordinario ING-INF/01 42 0 0 0 13
Co-lectuers
Espandi
Context
SSD CFU Activities Area context
ING-INF/01 6 F - Altre attività (art. 10) Abilità informatiche e telematiche
Statistiche superamento esami
2023/24
The course are taught in English. The subject is offered in the study tracks of Electronic Engineering Master where the technological knowledge of the integration processes is need, the subject is also compulsary in the study plan for Nanotechnologie for ICTs Master. The subject is offered during the first semester of the second year and is focused on the technological aspects of system integration with attention to micro and nano technologies currently available to the designers.
The course is mainly focused on technologies for scalable and heterogeneous integrated functionalities. Future breakthroughs require the study of new devices as well new materials and integration schemes: the knowledge of the relationships between technological processes, device structures and system performance is mandatory for electronic designers. The scaling for planar CMOS technologies during last years can be considered a successful example of the advancement of the technological processes that made possible the definition of 3D devices.In this scenario, the Integrated Systems Technology course will provide the skills enabling the student to understand the relations between physical models at the technological level, and the system level performance. The course will provide a wide range of technological competences, exploited in the practice classes to guarantee a sound quantitative comprehension, and in the simulation laboratories to allow a correct interpretation at the system level of the possible technological solutions.
-Classification of the most relevant CMOS fabrication processes in accordance to ITRS roadmap and their evaluation in terms of figures of merit (Ion, Ioff, intrinsic time....) -Evaluation of consequences due to the scaling techniques used in integration processes both on the single devices and on the inteconnects among structures. -Knowledge of the main fabrication technologies for nanometer scale devices: advanced gate and channel technologies. -Knowledge of adavanced CMOS processes as SOI, Double gate, FinFET, GAA. -Knowlege of the inteconnections and packaging technologies and evaluation of their electrical behavior in term of delays, crosstlak, IR drop. -Ability of using simulation tools for the estimation of the consequences on device and system of the technological parameters. -Knowledge of the emerging technologies that can be considered a possible replacement of CMOS processes.
-Classification of the most relevant CMOS fabrication processes in accordance to ITRS roadmap and their evaluation in terms of figures of merit (Ion, Ioff, intrinsic time....) -Evaluation of consequences due to the scaling techniques used in integration processes both on the single devices and on the inteconnects among structures. -Knowledge of the main fabrication technologies for nanometer scale devices: advanced gate and channel technologies. -Knowledge of adavanced CMOS processes as SOI, Double gate, FinFET, GAA. -Knowlege of the inteconnections and packaging technologies and evaluation of their electrical behavior in term of delays, crosstlak, IR drop. -Knowlege of the heterogenous and 3D integration technologies. -Ability of using simulation tools for the estimation of the consequences on device and system of the technological parameters. -Knowledge of the emerging technologies that can be considered a possible replacement of CMOS processes.
Good Knowledge of the basic technological processes used in planar technology as photolitography, doping, epitaxy, oxidation and film deposition. Deep knowledge of MOS systems and MOSFET devices: main equations for long and short channel devices with great care to the the conduction in velocity saturation and in subthreshold conditions. Electrical modelling of the intercconects in the integrated circuits.
Good Knowledge of the basic technological processes used in planar technology as photolitography, doping, epitaxy, oxidation and film deposition. Deep knowledge of MOS systems and MOSFET devices: main equations for long and short channel devices with great care to the conduction in saturation and in subthreshold conditions. Knowledge of the main short channel effects: threshold voltage roll-off and drain induced barrier lowering. Electrical modelling of the intercconects in the integrated circuits.
-Classification of the most used CMOS fabrication processes (HP High performance,LOP Low Operating Power, LSTP Low Stand By Power) -Technological scaling: analysis of the consequences at device level, at interconnects level and at system level. -Advanced CMOS processes: gate structures. -Advanced CMOS processes: channel and source drain structures. -FinFET and GAA technology. -Evaluation of the technological choices on the system level performance: frequency, dynamic power, static power. -Interconnects techniques: damascene, dual damascene, planarization and low-k dielectrics. -Packaging technologies. -Emerging technologies: fabrication of nano wires. -Emerging Tecnologies: 3D integration.
-Classification of the most used CMOS fabrication processes (HP High performance,LOP Low Operating Power, LSTP Low Stand By Power) -Technological scaling: analysis of the consequences at device level, at interconnects level and at system level. -Advanced CMOS processes: gate structures. -Advanced CMOS processes: channel and source drain structures. -FinFET and GAA technology. -Evaluation of the technological choices on the system level performance: frequency, dynamic power, static power. -Interconnects techniques: damascene, dual damascene, planarization and low-k dielectrics. -Packaging technologies. -Emerging technologies: fabrication of nano wire transistors, fabrication of tunnel fet. -Emerging Tecnologies: heterogeneous and 3D integration.
The practises will be focused on the evaluation of the main system parameters as function of the technological choices adopted during the system integration: in more details by mean of some cases of study will be studied a methodology to evaluate the system behavior from the device and inteconnects parameters both for CMOS processes and for 'emerging' technologies. Some laboratories based on MASTAR simulator will be assigned: starting from a standard process the student will modify its technological parameters to satisfy system level constraints. During the second part of the semester a mandatory project is assigned. The project will be developed by groups of students with the main aim of developimg a tool for the system level prediction.
The practises will be focused on the evaluation of the main system parameters as function of the technological choices adopted during the system integration: in more details by mean of some cases of study will be studied a methodology to evaluate the system behavior from the device and inteconnects parameters both for CMOS processes and for 'emerging' technologies. Some simulation laboratories will be assigned: starting from a standard process the student will modify its technological parameters to satisfy system level constraints. During the second part of the semester a mandatory project is assigned. The project will be developed by groups of students with the main aim of developing models for the system level prediction.
The main manual book used is the ITRS roadmap in web published version on http://www.itrs2.net. The most used sections are: Process Integration Devices and Structures; Interconnects; Assembly; Emerging Research Devices. Slides of lecture and some related scientific papers for insights are available on web pages of the subject.
The main manual book used is the ITRS roadmap in web published version on http://www.itrs2.net. The most used sections are: Process Integration Devices and Structures; Interconnects; Assembly; Emerging Research Devices. Slides of lecture and some related scientific papers for insights are available on web pages of the subject.
Modalità di esame: Prova scritta (in aula); Prova orale obbligatoria;
Exam: Written test; Compulsory oral exam;
... The exam is organized: 1)a brief (40 minutes) closed book written section where 7 questions with open answer (max. 100 words) will enable the student to go on the exam if at least 4/7 answers will be right; this section does not contribute to the final score; 2)a 30 minutes oral exam on the whole subjects (classes and practises) with the weight of 0.6 on the final score will be evaluated in /30; 3)a project work (assigned during the semester) will be presented and evaluated in /30 with a weight of 0.4.
Gli studenti e le studentesse con disabilità o con Disturbi Specifici di Apprendimento (DSA), oltre alla segnalazione tramite procedura informatizzata, sono invitati a comunicare anche direttamente al/la docente titolare dell'insegnamento, con un preavviso non inferiore ad una settimana dall'avvio della sessione d'esame, gli strumenti compensativi concordati con l'Unità Special Needs, al fine di permettere al/la docente la declinazione più idonea in riferimento alla specifica tipologia di esame.
Exam: Written test; Compulsory oral exam;
The exam is organized: 1)a brief (40 minutes) closed book written section where 7 questions with open answer (max. 100 words) will enable the student to go on the exam if at least 4/7 answers will be right; this section does not contribute to the final score; 2)a 30 minutes oral exam on the whole subjects (classes and practises) with the weight of 0.6 on the final score will be evaluated in /30; 3)a project work (assigned during the semester) will be presented and evaluated in /30 with a weight of 0.4.
In addition to the message sent by the online system, students with disabilities or Specific Learning Disorders (SLD) are invited to directly inform the professor in charge of the course about the special arrangements for the exam that have been agreed with the Special Needs Unit. The professor has to be informed at least one week before the beginning of the examination session in order to provide students with the most suitable arrangements for each specific type of exam.
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