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PORTALE DELLA DIDATTICA

Modeling and optimization of embedded systems

01NWNOV

A.A. 2023/24

Course Language

Inglese

Course degree

Master of science-level of the Bologna process in Ingegneria Informatica (Computer Engineering) - Torino

Course structure
Teaching Hours
Teachers
Teacher Status SSD h.Les h.Ex h.Lab h.Tut Years teaching
Teaching assistant
Espandi

Context
SSD CFU Activities Area context
ING-INF/01 6 C - Affini o integrative Attività formative affini o integrative
2022/23
The course is taught in English. This course introduces the main mathematical models and methods used for the synthesis and verification of embedded hardware and software. It assumes a good knowledge of digital hardware design (with VHDL or Verilog) and of software implementation (with C, C++ or Java) for embedded systems, including a basic knowledge of real-time operating systems. It provides the ability to select and use the best tools and methods for hardware/software co-design, as well as simulation and performance analysis. It provides knowledge about the SystemC language, synchronous languages and dataflow networks.
The course is taught in English. Embedded systems, including a mix of hardware and software and interacting continuously with the physical world, lie at the heart of the fourth industrial revolution, enabling unprecedented efficiency in mixed electronic, electrical and mechanical systems. Their effective implementation, in terms of performance, cost and energy, is thus essential to enable technological and economic progress in almost every domain of human activity. This course introduces the main mathematical models and methods used for the synthesis and verification of embedded hardware and software. It assumes a good knowledge of digital hardware design (with VHDL or Verilog) and of software implementation (with C, C++ or Java) for embedded systems, including a basic knowledge of microcontroller architectures. It provides the ability to select and use the best tools and methods for hardware/software co-design, as well as simulation and performance analysis. It provides knowledge about: - the SystemC language for mixed HW/SW modeling and verification, - synchronous languages for synthesis and verification of control-dominated embedded systems and - dataflow networks for synthesis and verification of data-dominated embedded systems.
• Knowledge of the main formal models and specification languages based on extended finite state machines and dataflow networks. • Knowledge of the hardware and software synthesis methods for synchronous languages and dataflow networks. • Knowledge of embedded software performance analysis techniques. • Ability to analyze at a high level the computational and communication requirements of an embedded application. • Ability to select the best specification languages and implementation tools, and to select a hardware/software architecture for an embedded system. • Ability to create a simulation model of an embedded system using a modeling language (e.g. SystemC).
• Knowledge of the main formal models and specification languages for embedded systems, based on C++ (SystemC), extended finite state machines (synchronous languages) and dataflow networks. • Knowledge of the hardware and software synthesis methods for synchronous languages and dataflow networks, including High-Level Synthesis of digital HW from C++. • Knowledge of embedded software performance analysis techniques. • Ability to analyze at a high level the computational and communication requirements of an embedded application. • Ability to select the best modeling languages and implementation tools, and to select a hardware/software architecture for an embedded system. • Ability to create a simulation model of an embedded system using a modeling language (e.g. SystemC).
• Digital hardware design using Verilog or VHDL • C, C++ or Java programming • Architecture of at least one CPU, memory architecture and micro-controller. • Micro-controller peripheral programming. • Elements of real-time schedulability theory.
• Digital hardware design using Verilog or VHDL • C, C++ or Java programming • Architecture of at least one micro-controller. • Micro-controller peripheral programming.
Topics (about 1/2 credit each): • Characteristics of embedded systems, architectures and design flows. • Control-dominated systems and data-dominated systems. • SystemC language: syntax and semantics. Usage examples. • SystemC design at Transaction level (TLM) and Register Transfer Level (RTL). • Dataflow networks: Kahn Process Networks, determinacy and schedulability. Usage examples. • Static scheduling of dataflow networks, minimizing code size or data memory size. • Hardware synthesis of dataflow networks. • Extended Finite State machines. Synchronous Moore and Mealy composition. • Synchronous languages: StateCharts, Esterel and ECL. Control constructs (emit, await, abort, parallel). Usage examples. • Hardware and software synthesis techniques for Esterel. Interfacing methods with operating systems and peripherals. • Formal property verification (liveness and safety) using synchronous languages. • Worst-Case Execution Time analysis for software via simulation and formal methods.
Topics (about 1/2 credit each): • Characteristics of embedded systems, architectures and design flows. • Control-dominated systems and data-dominated systems. • SystemC language: syntax and semantics. Usage examples. • SystemC design at Transaction level (TLM) and Register Transfer Level (RTL). • Dataflow networks: Kahn Process Networks, determinacy and schedulability. Usage examples. • Static scheduling of dataflow networks, minimizing code size or data memory size. • Hardware synthesis of dataflow networks from C++ via dataflow networks. • Extended Finite State machines. Synchronous Moore and Mealy composition. • Synchronous languages: StateCharts, Esterel and ECL. Control constructs (emit, await, abort, parallel). Usage examples. • Hardware and software synthesis techniques for Esterel. Interfacing methods with operating systems and peripherals. • Formal property verification using synchronous languages. • Worst-Case Execution Time analysis for software via simulation and formal methods.
Discussion sessions will reinforce concepts described during lessons and apply them to the solution of simple exercises, to be first solved individually and then discussed at the blackboard. Laboratory sessions will require the use of the SystemC language to model the functionality and performance of an embedded system, including both control-dominated and data-dominated aspects. Other laboratory sessions will teach the basics of high-level synthesis tool usage.
Exercises, to be first solved individually and then discussed interactively, will reinforce concepts described during the lessons. Laboratory sessions will require the use of the SystemC language to model the functionality and performance of an embedded system, including both control-dominated and data-dominated aspects. Other laboratory sessions will teach the basics of high-level synthesis tool usage. All laboratory sessions can be done remotely.
Peter Marwedel, “Embedded System Design”, Kluwer Academic Publishers, 2003. Maurizio Tranchero, Luciano Lavagno et al., “Modeling and Optimization of Embedded Systems”, available on “portale della didattica”. Slides used during lessons and laboratory guides, also available on “portale della didattica”.
Peter Marwedel, “Embedded System Design”, Kluwer Academic Publishers, 2003. Maurizio Tranchero, Luciano Lavagno et al., “Modeling and Optimization of Embedded Systems”, available on “portale della didattica”. Slides used during lessons and laboratory guides, also available on “portale della didattica”.
Modalità di esame: Prova orale facoltativa; Prova scritta in aula tramite PC con l'utilizzo della piattaforma di ateneo;
Exam: Optional oral exam; Computer-based written test in class using POLITO platform;
The final exam is composed of a written and an optional oral part. The written test includes both numerical exercises and multiple choice questions about the main topics of the course (SystemC, ECL, dataflow networks, worst case execution time analysis). It lasts 1.5-2 hours. Neither books nor notes can be used. The maximum score is 30. Examples of written tests from past years are posted on "portale della didattica". The oral can be requested by the student after seeing the graded written test, lasts for 15-20 minutes, and covers all the course topics. The final grade is a weighted average of the written and oral exam results, and can be 30 e lode after a very successful oral exam.
Gli studenti e le studentesse con disabilità o con Disturbi Specifici di Apprendimento (DSA), oltre alla segnalazione tramite procedura informatizzata, sono invitati a comunicare anche direttamente al/la docente titolare dell'insegnamento, con un preavviso non inferiore ad una settimana dall'avvio della sessione d'esame, gli strumenti compensativi concordati con l'Unità Special Needs, al fine di permettere al/la docente la declinazione più idonea in riferimento alla specifica tipologia di esame.
Exam: Optional oral exam; Computer-based written test in class using POLITO platform;
The final exam is composed of a mandatory PC-based exam and an optional oral part. The PC-based exam includes both numerical exercises and multiple choice questions about the main topics of the course as listed above, in particular: - SystemC: one open exercise writing code for a simple design, worth 10 points. Only modeling concepts will be evaluated, not the correctness of the syntax. - synchronous languages: 5 yes/no questions covering the legality of various construct combinations, each worth 1 point, without penalty for incorrect answers. - dataflow networks: 1 open numerical exercise, worth 5 points. Both the method used and the numerical answers will be evaluated. - theory: 5 multiple choice questions covering the theoretical parts of the course, each worth 2 point, with a 0.5 point penalty for incorrect answers. It lasts 90 minutes. Neither books nor notes can be used. The maximum score is 30. Examples of written tests from past years are posted on "portale della didattica". The optional oral exam can be requested by the student only if the PC-based exam is sufficient, lasts for 15-20 minutes, and covers all the course topics, with more emphasis on the theory. The final grade is a weighted average of the written (weight 0.7) and oral (weight 0.3) exam results, and can be 30 e lode after a very successful oral exam.
In addition to the message sent by the online system, students with disabilities or Specific Learning Disorders (SLD) are invited to directly inform the professor in charge of the course about the special arrangements for the exam that have been agreed with the Special Needs Unit. The professor has to be informed at least one week before the beginning of the examination session in order to provide students with the most suitable arrangements for each specific type of exam.
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