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Testing and fault tolerance

01RKZOV, 01RKZOQ, 01RKZQW

A.A. 2020/21

Course Language

Inglese

Course degree

Master of science-level of the Bologna process in Ingegneria Informatica (Computer Engineering) - Torino
Master of science-level of the Bologna process in Ingegneria Elettronica (Electronic Engineering) - Torino
Master of science-level of the Bologna process in Mechatronic Engineering (Ingegneria Meccatronica) - Torino

Course structure
Teaching Hours
Lezioni 40
Esercitazioni in aula 10
Esercitazioni in laboratorio 10
Tutoraggio 17,5
Teachers
Teacher Status SSD h.Les h.Ex h.Lab h.Tut Years teaching
Sonza Reorda Matteo Professore Ordinario ING-INF/05 40 10 0 0 7
Teaching assistant
Espandi

Context
SSD CFU Activities Area context
ING-INF/05 6 B - Caratterizzanti Ingegneria informatica
2020/21
The usage of electronic systems in applications where failures may results in critical consequences (e.g., in space, aircrafts, automobiles, trains, biomedical equipment) requires ensuring that the probability of a failure does not overcome some maximum threshold. This can be achieved by identifying and removing defective products (test) and by making products resilient to faults (fault tolerance). The course introduces methods and techniques for the design of reliable electronic circuits and systems, with special emphasis on the test performed to identify products affected by hardware faults, and on the solutions to harden electronic products with respect to faults and to the techniques to estimate the probability that possible faults may force them to produce failures.
The usage of electronic systems in applications where failures may results in critical consequences (e.g., in space, aircrafts, automobiles, trains, biomedical equipment) requires ensuring that the probability of a failure does not overcome some maximum threshold. This can be achieved by identifying and removing defective products (test) and by making products resilient to faults (fault tolerance). The course introduces methods and techniques for the design of reliable electronic circuits and systems, with special emphasis on the test performed to identify products affected by hardware faults, and on the solutions to harden electronic products with respect to faults and to the techniques to estimate the probability that possible faults may force them to produce failures.
- Knowledge of the concepts of testing and dependability. - Knowledge of the main techniques used for testing a digital circuit. - Knowledge of the main techniques used for testing an embedded system. - Knowledge of the basic techniques used for hardening an electronic products with respect to possible faults. - Knowledge of the main techniques for estimating the reliability of an electronic system. - Capability of developing the test plan for a digital device or embedded system - Capability to use the main software tools for testing an embedded system: fault simulators, automatic test pattern generators, automatic scan chain inserters. - Knowledge of the concept of Built-In Self-Test (BIST) and Boundary Scan (BS). - Knowledge of the concept of Failure Mode and Effect Analysis (FMEA). - Capability of designing BIST hardware modules.
- Knowledge of the concepts of testing and dependability. - Knowledge of the main techniques used for testing a digital circuit. - Knowledge of the main techniques used for testing an embedded system. - Knowledge of the basic techniques used for hardening an electronic products with respect to possible faults. - Knowledge of the main techniques for estimating the reliability of an electronic system. - Capability of developing the test plan for a digital device or embedded system - Capability to use the main software tools for testing an embedded system: fault simulators, automatic test pattern generators, automatic scan chain inserters. - Knowledge of the concept of Built-In Self-Test (BIST) and Boundary Scan (BS). - Knowledge of the concept of Failure Mode and Effect Analysis (FMEA). - Capability of designing BIST hardware modules.
The course is better followed if the student owns the knowledge about • Digital system design • Microelectronics.
The course is better followed if the student owns the knowledge about • Digital system design • Microelectronics.
1. Introduction to test and dependability (1 credit) a. Dependability: definition, attributes b. Fault models (temporary and transient): stuck-at, bridge, open, delay, SEU, SET c. Test of ICs, boards and systems d. Defect level: definition and evaluation e. ATEs 2. Techniques and tools for generating test stimuli for combinational and sequential modules (1 credit) a. Fault simulation b. Automatic Test Pattern Generation 3. Techniques and tools for testing specific modules (1 credit) a. Memory test b. Processor test 4. Design for Testability techniques (1 credit) a. Scan b. BIST c. Boundary Scan d. System on Chip test (IEEE 1500 and 1687) 5. Board test (0.5 credit) a. Main steps in PCB test b. IEEE 1149.1 6. Basics in fault tolerant system design (1.5 credits) a. Basic fault tolerant design solutions (hw redundancy, information redundancy, time redundancy) b. Reliability evaluation (FMEA, radiation experiments, fault injection)
1. Introduction to test and dependability (1 credit) a. Dependability: definition, attributes b. Fault models (temporary and transient): stuck-at, bridge, open, delay, SEU, SET c. Test of ICs, boards and systems d. Defect level: definition and evaluation e. ATEs 2. Techniques and tools for generating test stimuli for combinational and sequential modules (1 credit) a. Fault simulation b. Automatic Test Pattern Generation 3. Techniques and tools for testing specific modules (1 credit) a. Memory test b. Processor test 4. Design for Testability techniques (1 credit) a. Scan b. BIST c. Boundary Scan d. System on Chip test (IEEE 1500 and 1687) 5. Board test (0.5 credit) a. Main steps in PCB test b. IEEE 1149.1 6. Basics in fault tolerant system design (1.5 credits) a. Basic fault tolerant design solutions (hw redundancy, information redundancy, time redundancy) b. Reliability evaluation (FMEA, radiation experiments, fault injection)
Laboratory activities are an integral part of this course. During the lab sessions students will face the practical aspects introduced by lectures. Lab sessions will allow students to work with commercial tools for Fault Simulation, Scan Insertion, Automatic Test Pattern Generation and Boundary Scan test development. Students will also be asked to develop assignments concerning the course subjects. A typical assignment consists in implementing a given test solution (whose main characteristics have been described in the lectures) for a specific case study.
Laboratory activities are an integral part of this course. During the lab sessions students will face the practical aspects introduced by lectures. Lab sessions will allow students to work with commercial tools for Fault Simulation, Scan Insertion, Automatic Test Pattern Generation and Boundary Scan test development. Students will also be asked to develop assignments concerning the course subjects. A typical assignment consists in implementing a given test solution (whose main characteristics have been described in the lectures) for a specific case study.
Students may benefit of the following textbook: M. Bushnell, V. Agrawal: Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits Kluwer Academic Publisher, 2000 Slides will be provided to students registered to the course through the Student Teaching Portal, as well as any additional non-copyrighted information material that will be used in the course.
Students may benefit of the following textbook: M. Bushnell, V. Agrawal: Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits Kluwer Academic Publisher, 2000 Slides will be provided to students registered to the course through the Student Teaching Portal, as well as any additional non-copyrighted information material that will be used in the course.
Modalità di esame: Prova orale obbligatoria; Prova scritta tramite PC con l'utilizzo della piattaforma di ateneo; Elaborato progettuale in gruppo;
The exam will be based on - a written part in which the students will be asked to answer to some (about 6) questions and exercises. The written exam will last for about 60 minutes and provides a score between 0 and 15. The written part is passed if the score is at least 9. - an oral part (only for students who passed the written part). The students will be allowed to make an assignment which could increase the score of the exam by up to 5 points. The additional points stemming from the possible assignment are added to the exam score only if the latter is at least 18.
Exam: Compulsory oral exam; Computer-based written test using the PoliTo platform; Group project;
The exam will be based on - a written part in which the students will be asked to answer to some (about 6) questions and exercises. The written exam will last for about 60 minutes and provides a score between 0 and 15. The written part is passed if the score is at least 9. - an oral part (only for students who passed the written part). The students will be allowed to make an assignment which could increase the score of the exam by up to 5 points. The additional points stemming from the possible assignment are added to the exam score only if the latter is at least 18.
Modalità di esame: Prova scritta (in aula); Prova orale obbligatoria; Prova scritta tramite PC con l'utilizzo della piattaforma di ateneo; Elaborato progettuale in gruppo;
The exam will be based on - a written part in which the students will be asked to answer to some (about 6) questions and exercises. The written exam will last for about 60 minutes and provides a score between 0 and 15. The written part is passed if the score is at least 9. - an oral part (only for students who passed the written part). The students will be allowed to make an assignment which could increase the score of the exam by up to 5 points. The additional points stemming from the possible assignment are added to the exam score only if the latter is at least 18.
Exam: Written test; Compulsory oral exam; Computer-based written test using the PoliTo platform; Group project;
The exam will be based on - a written part in which the students will be asked to answer to some (about 6) questions and exercises. The written exam will last for about 60 minutes and provides a score between 0 and 15. The written part is passed if the score is at least 9. - an oral part (only for students who passed the written part). The students will be allowed to make an assignment which could increase the score of the exam by up to 5 points. The additional points stemming from the possible assignment are added to the exam score only if the latter is at least 18.
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