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Micro and Nanoelectronic Devices

01UAXPE, 01UAXOQ

A.A. 2022/23

Course Language

Inglese

Course degree

Master of science-level of the Bologna process in Nanotechnologies For Icts (Nanotecnologie Per Le Ict) - Torino/Grenoble/Losanna
Master of science-level of the Bologna process in Ingegneria Elettronica (Electronic Engineering) - Torino

Course structure
Teaching Hours
Lezioni 40
Esercitazioni in laboratorio 20
Teachers
Teacher Status SSD h.Les h.Ex h.Lab h.Tut Years teaching
Donati Guerrieri Simona Professore Associato ING-INF/01 40 0 20 0 4
Teaching assistant
Espandi

Context
SSD CFU Activities Area context
ING-INF/01 6 B - Caratterizzanti Ingegneria elettronica
Valutazione CPD 2021/22
2022/23
The course is taught in English. The course aims at providing a solid knowledge on the operation of the main semiconductor devices for the micro and nanoelectronics applications. The first part of the course is dedicated to the evolution of the MOS transistor technology, with emphasis on the CMOS applications. The FinFET transistor is addressed both from the technological and the modeling standpoint. The second part of the course is dedicated to emerging nanoelectronic devices, with particular emphasis on CMOS replacement and novel memory/storage devices, including the junctionless transistors, the tunneling transistors and lower dimensionality structures. The course provides the fundamentals for understanding the devices operation, starting from their physical structure and using the concepts of the semiconductor physics. The devices are analyzed at all levels, starting from the fabrication process, the modeling and simulation through CAD tools, highlighting the problems related to non-idealities and scaling issues.
The course is taught in English. The course aims at providing a solid knowledge on the operation of the main semiconductor devices for the micro and nanoelectronics applications. The first part of the course is dedicated to the evolution of the MOS transistor technology, with emphasis on the CMOS applications. The FinFET transistor is addressed both from the technological and the modeling standpoint. The second part of the course is dedicated to emerging nanoelectronic devices, with particular emphasis on CMOS replacement and novel memory/storage devices, including the junctionless transistors, the tunneling transistors and lower dimensionality structures. The course provides the fundamentals for understanding the devices operation, starting from their physical structure and using the concepts of the semiconductor physics. The devices are analyzed at all levels, starting from the fabrication process, the modeling and simulation through CAD tools, highlighting the problems related to non-idealities and scaling issues.
As the outcome of the course, students will be able to - Analyze the behavior of the micro- and nano- scale devices, including the related problematic linked to geometric scaling and technology fabrication issues - Identify the correct models for representation of the electron device behavior, both through analytic/compact models anfd through technology CAD software (Synopsys Sentaurus). - Include the main non-ideality effects into the models (high field, multi-dimensionality, quantum effects, quantum confinement), and link their solution to the main developments of the fabrication technology. - Identify the correct modeling approach for the nano-scale devices - Orient their knowledge and future work within the scenario of the nanoelectronic device research field, with solid background on the problems that still need for solution, the future needs and expected developments both at the technology level and in the area of advanced modeling.
As the outcome of the course, students will be able to - Analyze the behavior of the micro- and nano- scale devices, including the related problematic linked to geometric scaling and technology fabrication issues - Identify the correct models for representation of the electron device behavior, both through analytic/compact models anfd through technology CAD software (Synopsys Sentaurus). - Include the main non-ideality effects into the models (high field, multi-dimensionality, quantum effects, quantum confinement), and link their solution to the main developments of the fabrication technology. - Identify the correct modeling approach for the nano-scale devices - Orient their knowledge and future work within the scenario of the nanoelectronic device research field, with solid background on the problems that still need for solution, the future needs and expected developments both at the technology level and in the area of advanced modeling.
Students must already have a solid background on the semiconductor physics, and in particular on the drift-diffusion model. Furthermore they must have previous knowledge on the fundamental operation of electron devices and in particular of the MOS transisitor.
Students must already have a solid background on the semiconductor physics, and in particular on the drift-diffusion model. Furthermore they must have previous knowledge on the fundamental operation of electron devices and in particular of the MOS transisitor.
- Technology roadmaop and physical limitations of miniaturization. Scenario of the micro- an nano-electronics. (0.45 credits). - Advanced modelling for the MOS transistor. (0.9 credits) - Submicron MOSFET: scaling and nonidealities issues (0.9 credits) - FinFETs (0.6 credits) - Junctionless, Tunneling and Negative Capacitance transistors (0.6 credits) - Emerging technologies (0.6 credits) - Assisted laboratory practice using a commercial CAD tool for the physics-based simulation of semiconductor devices. (1.95 credits)
- Technology roadmaop and physical limitations of miniaturization. Scenario of the micro- an nano-electronics. (0.45 credits). - Advanced modelling for the MOS transistor. (0.9 credits) - Submicron MOSFET: scaling and nonidealities issues (0.9 credits) - FinFETs (0.6 credits) - Junctionless, Tunneling and Negative Capacitance transistors (0.9 credits) - Emerging technologies (0.3 credits) - Assisted laboratory practice using a commercial CAD tool for the physics-based simulation of semiconductor devices. (1.95 credits)
Technical notes on the course for CORONA emergency. Remote teaching: - Lesson: lessons will be partly offline (theory and demonstrations) and partly interactive using the Virtual Classroom Platform (question and answers, exercise). - LAB: LAB will be entirely online using the Virtual Classroom Platform. The group members can interact and work collectively using the Virtual Classroom breakout rooms. A server is available for simulations. Blended teaching: - Lesson: lessons will be partly offline (theory and demonstrations) and partly on site (Politecnico campus) for Q&A and exercise. The on-site lessons will be in any case available also remotely. - LAB: LAB will be partly in the LED facilities of Politecnico and partly online using the Virtual Classroom Platform. Even during the on-site labs, those, who cannot attend, will be able to interact and work both individually and collectively with their group mates using the Virtual Classroom platform. A server is available for simulations. To assist the theory part, teachers notes will be made available for individual study.
Technical notes on the course for CORONA emergency. Remote teaching: - Lesson: lessons will be partly offline (theory and demonstrations) and partly interactive using the Virtual Classroom Platform (question and answers, exercise). - LAB: LAB will be entirely online using the Virtual Classroom Platform. The group members can interact and work collectively using the Virtual Classroom breakout rooms. A server is available for simulations. Blended teaching: - Lesson: lessons will be partly offline (theory and demonstrations) and partly on site (Politecnico campus) for Q&A and exercise. The on-site lessons will be in any case available also remotely. - LAB: LAB will be partly in the LED facilities of Politecnico and partly online using the Virtual Classroom Platform. Even during the on-site labs, those, who cannot attend, will be able to interact and work both individually and collectively with their group mates using the Virtual Classroom platform. A server is available for simulations. To assist the theory part, teachers notes will be made available for individual study.
4 credits of theoretical lessons. 2 credits of assisted CAD laboratory practice using a commercial CAD tool for the physics-based simulation of semiconductor devices. There will be two LAB groups, following the same introduction part (advanced CMOS) and a different second part on specific applications: one LAB group will be dedicated to FinFETs; the other to selected beyond CMOS nanodevices.
4 credits of theoretical lessons. 2 credits of assisted CAD laboratory practice using a commercial CAD tool for the physics-based simulation of semiconductor devices. The LAB work will be in groups. The first 4 labs will be common to all students, including advanced CMOS and FinFETs. In the last 2 labs each group will be assigned a specific topic on advanced technologies, either advanced FinFETs or other selected beyond CMOS nanodevices.
Reference textbook: Yuan Taur, Tak H. Ning Fundamentals of modern VLSI devices Cambridge University Press 2nd edition Teaching material from the professor: - Review of the semiconductor physics required as the background knowledge for this course (self-learning) - Course slides - Guidelines for the lab work -Further material for advanced topics
Reference textbook: Yuan Taur, Tak H. Ning Fundamentals of modern VLSI devices Cambridge University Press 2nd edition Teaching material from the professor: - Review of the semiconductor physics required as the background knowledge for this course (self-learning) - Course slides - Guidelines for the lab work -Further material for advanced topics
Modalità di esame: Prova orale obbligatoria; Elaborato progettuale in gruppo;
Exam: Compulsory oral exam; Group project;
The final exam consists of an oral exam (30 min.) and a laboratory test (15 min.). The oral exam aims at assessing the knowledge of the theoretical part whereas the laboratory test is aimed at assessing the capability gained in the numerical simulation of advanced electron devices. The Lab test includes always the discussion of the laboratory reports prepared in groups. The oral exam vote is up to 25. The lab vote, up to 5 points, summarizes the evaluation of the written laboratory reports (group-wise) and the individual lab exam. The exam is passed only if both the oral and lab parts are sufficient.
Gli studenti e le studentesse con disabilità o con Disturbi Specifici di Apprendimento (DSA), oltre alla segnalazione tramite procedura informatizzata, sono invitati a comunicare anche direttamente al/la docente titolare dell'insegnamento, con un preavviso non inferiore ad una settimana dall'avvio della sessione d'esame, gli strumenti compensativi concordati con l'Unità Special Needs, al fine di permettere al/la docente la declinazione più idonea in riferimento alla specifica tipologia di esame.
Exam: Compulsory oral exam; Group project;
The final exam consists of an oral exam (30 min.) and an oral discussion on laboratory activity (15 min.). The oral exam aims at assessing the knowledge of the theoretical part whereas the laboratory test is aimed at assessing the capability gained in the numerical simulation of advanced electron devices. The Lab test includes always the discussion of the laboratory reports prepared in groups. The oral exam vote is up to 25. The lab vote, up to 5 points, summarizes the evaluation of the written laboratory reports (group-wise) and the individual lab exam. The exam is passed only if both the oral and lab parts are sufficient.
In addition to the message sent by the online system, students with disabilities or Specific Learning Disorders (SLD) are invited to directly inform the professor in charge of the course about the special arrangements for the exam that have been agreed with the Special Needs Unit. The professor has to be informed at least one week before the beginning of the examination session in order to provide students with the most suitable arrangements for each specific type of exam.
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