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Integrated systems architecture

02GQCOQ

A.A. 2022/23

Course Language

Inglese

Course degree

Master of science-level of the Bologna process in Ingegneria Elettronica (Electronic Engineering) - Torino

Course structure
Teaching Hours
Lezioni 33
Esercitazioni in laboratorio 27
Tutoraggio 20
Teachers
Teacher Status SSD h.Les h.Ex h.Lab h.Tut Years teaching
Masera Guido Professore Ordinario ING-INF/01 33 0 0 0 19
Teaching assistant
Espandi

Context
SSD CFU Activities Area context
ING-INF/01 6 B - Caratterizzanti Ingegneria elettronica
2022/23
The course is taught in English. The course is part of the Msc-level programme in Electronic Engineering, offered in the first period of the second year. In particular, it completes the education of students with interest in the design of digital circuits and systems. The main objective of the course is providing techniques for the design of advanced digital processing architectures. Both programmable systems, such as modern microprocessors, and fully dedicated or application specific designs (ASIC) are considered. Among programmable systems, this course mainly superscalar and instruction level parallel (ILP) microprocessors. Design methodologies are provided to develop and optimize application specific architectures, starting from the initial specifications and arriving to the complete layout of the circuit. The main design issues for arithmetic circuits and on-chip interconnect are also studied. A very important role in the course is played by laboratory activities, which are based on the use of advanced design tools for integrated circuits.
The course is part of the MS-level programme in Electronic Engineering, offered in the first period of the second year. In particular, it completes the education of students with a specific interest in the design of complex digital circuits and systems. In this area, the course provides the fundamental techniques and knowledge for the design of advanced digital processing architectures. Both programmable systems, such as modern microprocessors, and fully dedicated or application-specific designs (ASIC) are considered. Among programmable systems, this course mainly deals with superscalar and instruction-level parallel (ILP) microprocessors. Design methodologies are provided to develop and optimize application-specific architectures, starting from the initial specifications and arriving to the complete layout of the circuit. The main design issues for arithmetic circuits and on-chip interconnect are also studied. A very important role in the course is played by laboratory activities, which are based on the use of advanced design tools for integrated circuits. Therefore, students who are not able to attend laboratory activities (onsite or online) are not encouraged to take this course. The course is taught in English.
Knowledge of high abstraction level design methodologies for digital integrated systems Knowledge of microprocessor architectures Knowledge of design tools based on HDL languages (VHDL, Verilog, System C) Knowledge and ability in the design of basic blocks used in integrated processing architectures, such as arithmetic circuits, memory architectures, interfaces, and interconnections Capability of designing a digital integrated circuit, from initial specifications down to post-layout verification Capability of reading and learning from a scientific paper Capability of writing a technical design report
Applying high abstraction level design methodologies for the description of digital integrated systems Understanding microprocessor architectures Using modern CAD design tools based on HDL languages (VHDL, Verilog, System C) Designing basic blocks used in integrated processing architectures, such as arithmetic circuits, memory architectures, interfaces, and interconnections Designing a digital integrated circuit, from initial specifications down to post-layout verification Reading and learning from a scientific/technical paper Writing a technical design report
Basics on digital circuits as learned in the first Digital electronics module of the Msc-level programme: Combinatorial and sequential circuits techniques; Control unit design, Timing issues, Complex processing architectures, Memories and interconnections, VHDL language and simulation tools
Basics on digital circuits as learned in the first Digital electronics module of the MS-level programme: Combinatorial and sequential circuits techniques; Control unit design, Timing issues, Complex processing architectures, Memories and interconnections, VHDL language and basic synthesis/simulation tools.
The course includes four main topics: 1. Methods for algorithm to architecture mapping (1.5 CFU) These methods (e.g. pipelining, retiming, folding, unfolding) are based on graph representation of algorithm and enable the exploration of alternative implementation architectures, with different cost and performance. Digital filters are used as driving examples. 2. Microprocessor architectures (2 CFU) Review of pipelined architectures (MIPS); A quantitative and qualitative study of superpipelined, superscalar, dataflow, and VLIW processors; Available parallelism in programs; Out of order instruction execution; Reservation stations; Reorder buffers; Branch prediction techniques; Performance evaluation; Multicore processors; Customizable processors. 3. Design of arithmetic circuits (1.5 CFU) Adders, Multipliers, Hardware division, Square root 4. On-chip interconnects (1 CFU) Bus basics, Examples of on-chip busses, Networks-on-Chip (NoC)
The course includes four main topics: 1. Methods for algorithm to architecture mapping (1.5 CFU) These methods (e.g. pipelining, retiming, folding, unfolding) are based on graph representation of algorithm and enable the exploration of alternative implementation architectures, with different cost and performance. Digital filters are used as driving examples. 2. Microprocessor architectures (2 CFU) Review of pipelined architectures (MIPS); A quantitative and qualitative study of superpipelined, superscalar, dataflow, and VLIW processors; Available parallelism in programs; Out of order instruction execution; Reservation stations; Reorder buffers; Branch prediction techniques; Performance evaluation; Multicore processors; Customizable processors. 3. Design of arithmetic circuits (1.5 CFU) Adders, Multipliers, Hardware division, Square root 4. On-chip interconnects (1 CFU) Bus basics, Examples of on-chip busses, Networks-on-Chip (NoC)
A very important role in the course is played by laboratory activities (three hours per week), which are based on the use of advanced design tools for integrated circuits. Design teams with two or three students each are formed and they have to complete assigned projects on three cases of studies: 1. VHDL to layout design of an application specific processing unit Design entry: structural VHDL Tools: Synopsys + Encounter 2. Design of a customizable processor Design entry: C language and behavioural VHDL Tools: TTA-based Co-design Environment (TCE) + VHDL tools 3. SystemC design Design entry: SystemC Tools: VHDL and SystemC co-simulation (Modelsim) Assigned projects must be completed before the end of the course. Obtained results must be described in written reports, which are evaluated to determine the final grade.
A very important role in the course is played by laboratory activities (three hours per week), which are based on the use of advanced design tools for integrated circuits. Design teams with two or three students each are formed and they have to complete assigned projects on three cases of studies: 1. VHDL to layout design of an application specific processing unit Design entry: structural VHDL Tools: Synopsys + Encounter 2. Design of a customizable processor Design entry: C language and behavioural VHDL Tools: TTA-based Co-design Environment (TCE) + VHDL tools 3. SystemC design Design entry: SystemC Tools: VHDL and SystemC co-simulation (Modelsim) Assigned projects must be completed before the end of the course. Obtained results must be described in written reports, which are evaluated to determine the final grade.
The learning material used for both lectures and laboratory sessions is made available through the course website: this material includes notes provided by teachers, slides, scientific papers and book chapters. Reference books that cover part of the course content are: David A. Patterson, John L. Hennessy, Computer Organization and Design RISC-V Edition,Morgan Kaufmann , 2017 K.K. Parhi, VLSI Digital Signal ProcessingSystems: Design and Implementation, John Wiley, 1999
The learning material used for both lectures and laboratory sessions is made available through the course website: this material includes notes provided by teachers, slides, scientific papers and book chapters. There are three reference textbooks covering the three main topics of the course: David A. Patterson, John L. Hennessy, Computer Organization and Design RISC-V Edition,Morgan Kaufmann , 2017 K.K. Parhi, VLSI Digital Signal ProcessingSystems: Design and Implementation, John Wiley, 1999 B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs, 2nd edition, Oxford University Press, New York, 2010 Very detailed slides from the latter textbook are available from the companion web site: https://web.ece.ucsb.edu/~parhami/text_comp_arch.htm.
ModalitÓ di esame: Prova scritta (in aula); Prova orale facoltativa; Elaborato progettuale in gruppo;
Exam: Written test; Optional oral exam; Group project;
... The final grade is formed from two components: 1. Evaluation of the written test (80%), up to 24 points 2. Project evaluation plus short oral colloquium related to the submitted projects (20%), up to 6 points After the written test, students can ask for an optional oral exam focused on the topics covered by lectures. This oral exam may change the first mark by plus/minus 3 points. The written test includes one or two brief design problems, as well as two or three open answer questions on the topics covered by lectures. Normally, the same weight is assigned to each question in the test; however, the weight of questions with very low average results can be slightly reduced. Available time is two hours. Use of books or notes is not admitted. Projects are evaluated based on the following criteria: - completeness of the design - adopted methodology - achieved results. The oral colloquium aims at clarifying design choices and other details of the submitted project; moreover, it is used the verify that every component of the team actually contributed to the design.
Gli studenti e le studentesse con disabilitÓ o con Disturbi Specifici di Apprendimento (DSA), oltre alla segnalazione tramite procedura informatizzata, sono invitati a comunicare anche direttamente al/la docente titolare dell'insegnamento, con un preavviso non inferiore ad una settimana dall'avvio della sessione d'esame, gli strumenti compensativi concordati con l'UnitÓ Special Needs, al fine di permettere al/la docente la declinazione pi¨ idonea in riferimento alla specifica tipologia di esame.
Exam: Written test; Optional oral exam; Group project;
The final grade is formed from two components: 1. Evaluation of the written test (70%), up to 21 points 2. Project evaluation plus short oral colloquium related to the submitted projects (30%), up to 9 points After the written test, students can ask for an optional oral exam focused on the topics covered by lectures. This oral exam may change the first mark by plus/minus 3 points. The written test includes one or two brief design problems, as well as two or three open answer questions on the topics covered by lectures. Normally, the same weight is assigned to each question in the test; however, the weight of questions with very low average results can be slightly reduced. Available time is two hours. Use of books or notes is not admitted. Projects are evaluated based on the following criteria: - completeness of the design - adopted methodology - achieved results. The oral colloquium aims at clarifying design choices and other details of the submitted project; moreover, it is used the verify that every component of the team actually contributed to the design.
In addition to the message sent by the online system, students with disabilities or Specific Learning Disorders (SLD) are invited to directly inform the professor in charge of the course about the special arrangements for the exam that have been agreed with the Special Needs Unit. The professor has to be informed at least one week before the beginning of the examination session in order to provide students with the most suitable arrangements for each specific type of exam.
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