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PORTALE DELLA DIDATTICA

Specification and simulation of digital systems

02LQDOV

A.A. 2019/20

Course Language

English

Course degree

Master of science-level of the Bologna process in Computer Engineering - Torino

Course structure
Teaching Hours
Lezioni 42
Esercitazioni in aula 18
Tutoraggio 80
Teachers
Teacher Status SSD h.Les h.Ex h.Lab h.Tut Years teaching
Camurati Paolo Enrico Professore Ordinario ING-INF/05 42 0 0 60 13
Teaching assistant
Espandi

Context
SSD CFU Activities Area context
ING-INF/05 6 B - Caratterizzanti Ingegneria informatica
2019/20
Course appearing in the tracks Embedded Systems and Software and Digital Systems). Students acquire the skills to describe digital systems at various levels of abstraction with the VHDL language. The Verilog language is introduced by difference. The course completes the design methodologies acquired in previous basic digital design courses and extends them to the register-transfer level. The course uses simulation-based verification techniques to develop in a lab several RT-level designs and deals with verification techniques based on formal methods, in particular combinational and sequential equivalence check and model checking. The course introduces the basic knowledge on testing digital circuits.
Course appearing in the tracks Embedded Systems and Software and Digital Systems). Students acquire the skills to describe digital systems at various levels of abstraction with the VHDL language. The Verilog language is introduced by difference. The course completes the design methodologies acquired in previous basic digital design courses and extends them to the register-transfer level. The course uses simulation-based verification techniques to develop in a lab several RT-level designs and deals with verification techniques based on formal methods, in particular combinational and sequential equivalence check and model checking. The course introduces the basic knowledge on testing digital circuits.
• Knowledge of the syntax and semantics of VHDL • Ability to describe complex digital systems in VHDL at various levels of abstraction • Basic knowledge of the Verilog language by difference w.r.t. VHDL • Knowledge of the fundamental features of embedded systems • Knowledge of the metrics to evaluate designs • Knowledge of the design methodologies for register-transfer level systems • Ability to design complex digital systems at the register-transfer level with CAD tools • Ability to verify by simulation complex digital system designs • Knowledge of the main formal verification techniques with particular emphasis on combinational and sequential equivalence check and model checking
• Knowledge of the syntax and semantics of VHDL • Ability to describe complex digital systems in VHDL at various levels of abstraction • Basic knowledge of the Verilog language by difference w.r.t. VHDL • Knowledge of the fundamental features of embedded systems • Knowledge of the metrics to evaluate designs • Knowledge of the design methodologies for register-transfer level systems • Ability to design complex digital systems at the register-transfer level with CAD tools • Ability to verify by simulation complex digital system designs • Knowledge of the main formal verification techniques with particular emphasis on combinational and sequential equivalence check and model checking
Knowledge of basic design techniques for combinational and synchronous sequential circuits.
Knowledge of basic design techniques for combinational and synchronous sequential circuits.
• VHDL: structure of VHDL files: entity/architecture; description styles: behavioral, dataflow, structural; lexical elements; objects: signals, variables and constants; data types: scalar types, composite types; operators and attributes; concurrent statements: concurrent signal assignments, generate statements, concurrent processes, component instantiations; sequential statements: processes, conditional statements, iterative statements; partitioning techniques: blocks, packages, libraries, components, configurations. Examples of combinational, synchronous and basic register-transfer level designs in VHDL. • Register Transfer-level embedded systems design: design metrics and their optimization; key technologies for embedded systems: processor technology, IC technology, design technology; single-purpose processor design: High-Level State Machines, the FSM-D model, from the algorithm to the FSM-D, synthesis of the datapath, synthesis of the control unit, description in VHDL; optimization of single-purpose processors: algorithm, FSM-D, datapath, FSM; optimization of Finite State Machines (FSMs): state minimization (simplified and exact equivalent state detection algorithm), state encoding heuristics. • Formal verification: approaches to design verification: simulation vs. formal verification; theorem proving: propositional logic, first-order logic, higher-order logic; equivalence checking: Binary Decision Diagrams, combinational equivalence check, sequential equivalence check (symbolic reachability analysis, the product machine model); Model Checking: linear-time temporal logic, branching-time temporal logic, liveness and safety properties, model checking algorithms. • Verilog by difference w.r.t. VHDL: descriptions of combinational circuits, sequential circuits and RTL designs.
• VHDL: structure of VHDL files: entity/architecture; description styles: behavioral, dataflow, structural; lexical elements; objects: signals, variables and constants; data types: scalar types, composite types; operators and attributes; concurrent statements: concurrent signal assignments, generate statements, concurrent processes, component instantiations; sequential statements: processes, conditional statements, iterative statements; partitioning techniques: blocks, packages, libraries, components, configurations. Examples of combinational, synchronous and basic register-transfer level designs in VHDL. • Register Transfer-level embedded systems design: design metrics and their optimization; key technologies for embedded systems: processor technology, IC technology, design technology; single-purpose processor design: High-Level State Machines, the FSM-D model, from the algorithm to the FSM-D, synthesis of the datapath, synthesis of the control unit, description in VHDL; optimization of single-purpose processors: algorithm, FSM-D, datapath, FSM; optimization of Finite State Machines (FSMs): state minimization (simplified and exact equivalent state detection algorithm), state encoding heuristics. • Formal verification: approaches to design verification: simulation vs. formal verification; theorem proving: propositional logic, first-order logic, higher-order logic; equivalence checking: Binary Decision Diagrams, combinational equivalence check, sequential equivalence check (symbolic reachability analysis, the product machine model); Model Checking: linear-time temporal logic, branching-time temporal logic, liveness and safety properties, model checking algorithms. • Verilog by difference w.r.t. VHDL: descriptions of combinational circuits, sequential circuits and RTL designs.
Lectures (40h) covering the syllabus + 20h lab work: students work with the Xilinx® Vivado HLS package to develop RT-level designs according to the methodologies described in the lectures. An optional short assignment is available. It is an individual project, assigned mid-December, to be handed in for evaluation before the oral exam and no later than the end of February exam session. It entails max 2/30 bonus on the final mark.
Lectures (40h) covering the syllabus + 20h lab work: students work with the Xilinx® Vivado HLS package to develop RT-level designs according to the methodologies described in the lectures. An optional short assignment is available. It is an individual project, assigned mid-December, to be handed in for evaluation before the oral exam and no later than the end of February exam session. It entails max 2/30 bonus on the final mark.
Handouts published on the course site. Additional readings: • F. Vahid, “Digital Design with RTL design, VHDL and Verilog”, 2nd edition, John Wiley, 2010 • D. Pellerin, D. Taylor “VHDL Made easy!”, Prentice Hall 1997 • F. Vahid, T. Givargis “Embedded System Design: a unified hardware/software introduction”, John Wiley, 2002 • M.Ercegovac, T. Lang, J. Moreno “Introduction to digital systems”, John Wiley, 1999 •
Handouts published on the course site. Additional readings: • F. Vahid, “Digital Design with RTL design, VHDL and Verilog”, 2nd edition, John Wiley, 2010 • D. Pellerin, D. Taylor “VHDL Made easy!”, Prentice Hall 1997 • F. Vahid, T. Givargis “Embedded System Design: a unified hardware/software introduction”, John Wiley, 2002 • M.Ercegovac, T. Lang, J. Moreno “Introduction to digital systems”, John Wiley, 1999 •
Modalità di esame: prova scritta; prova orale obbligatoria;
The exam consists in a written and in an oral part. Written exam (max 150 minutes): designs on paper of combinational networks, Finite State Machines and RT-level complex systems described in VHDL. Number of exercises varies according to difficulty. No books, slides or any other material allowed, except a VHDL primer. The goal of the written part is to ascertain that the student has acquired the ability to design complex digital systems and to describe them in VHDL at various levels of abstraction. Evaluation criteria: understanding of specifications, functional completeness of solution, correctness of VHDL code. No later than 3 days after the written exam, the student has to upload a simulable VHDL file and its testbench, as well as a short report focusing on the design choices and on the differences between the version handed in at the written exam and the uploaded one. If the VHDL files are uploaded before the deadline, the written exam is corrected and ranked. If the mark is sufficient (>= 15), follows a mandatory oral exam on all the topics dealt with during the course. Questions concern knowledge (definitions, concepts, etc.) and short exercises (in particular related to formal verification and Verilog). The oral exam aims at ascertaining that the student has acquired the notions in Formal Verification and Verilog that are part of the course syllabus. The final mark takes into account the results both in the written and the oral parts as a whole and not as an average. An optional short assignment is available. It is an individual project, assigned mid-December, to be handed in for evaluation before the oral exam and no later than the end of February exam session. It entails max 2/30 bonus on the final mark.
Exam: written test; compulsory oral exam;
The exam consists in a written and in an oral part. Written exam (max 150 minutes): designs on paper of combinational networks, Finite State Machines and RT-level complex systems described in VHDL. Number of exercises varies according to difficulty. No books, slides or any other material allowed, except a VHDL primer. The goal of the written part is to ascertain that the student has acquired the ability to design complex digital systems and to describe them in VHDL at various levels of abstraction. Evaluation criteria: understanding of specifications, functional completeness of solution, correctness of VHDL code. No later than 3 days after the written exam, the student has to upload a simulable VHDL file and its testbench, as well as a short report focusing on the design choices and on the differences between the version handed in at the written exam and the uploaded one. If the VHDL files are uploaded before the deadline, the written exam is corrected and ranked. If the mark is sufficient (>= 15), follows a mandatory oral exam on all the topics dealt with during the course. Questions concern knowledge (definitions, concepts, etc.) and short exercises (in particular related to formal verification and Verilog). The oral exam aims at ascertaining that the student has acquired the notions in Formal Verification and Verilog that are part of the course syllabus. The final mark takes into account the results both in the written and the oral parts as a whole and not as an average. An optional short assignment is available. It is an individual project, assigned mid-December, to be handed in for evaluation before the oral exam and no later than the end of February exam session. It entails max 2/30 bonus on the final mark.


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