02LQDOV

A.A. 2022/23

Course Language

Inglese

Course degree

Master of science-level of the Bologna process in Ingegneria Informatica (Computer Engineering) - Torino

Course structure

Teaching | Hours |
---|---|

Lezioni | 40 |

Esercitazioni in aula | 20 |

Tutoraggio | 40 |

Teachers

Teacher | Status | SSD | h.Les | h.Ex | h.Lab | h.Tut | Years teaching |
---|---|---|---|---|---|---|---|

Camurati Paolo Enrico | Professore Ordinario | ING-INF/05 | 40 | 0 | 0 | 20 | 16 |

Teaching assistant

Context

SSD | CFU | Activities | Area context |
---|---|---|---|

ING-INF/05 | 6 | C - Affini o integrative | Attività formative affini o integrative |

2022/23

Course appearing in the tracks Embedded Systems and Software and Digital Systems). Students acquire the skills to describe digital systems at various levels of abstraction with the VHDL language. The Verilog language is introduced by difference. The course completes the design methodologies acquired in previous basic digital design courses and extends them to the register-transfer level. The course uses simulation-based verification techniques to develop in a lab several RT-level designs and deals with verification techniques based on formal methods, in particular combinational and sequential equivalence check and model checking. The course introduces the basic knowledge on testing digital circuits.

Computing systems are everywhere in nowadays life, but when we think of them, most of us think of “desktop” computers, like PCs, laptops, mainframes and servers. But there is another type of computing systems that is far more common: embedded computing systems. They are computing systems embedded within electronic devices, intuitively nearly any computing system other than a desktop computer. Their main features are:
• billions of units produced yearly, versus millions of desktop units
• several tens, maybe hundreds, per household and per automobile
• they are:
• single-functioned as they execute a single program, repeatedly
• tightly-constrained in terms of low cost, low power, small size, speed, etc.
• reactive and real-time, as they continually reacts to changes in the system’s environment and must compute
results in real-time without delay
Designing embedded systems requires:
• knowledge of what the hardware is and does (combinational circuits, sequential circuits, Finite State Machines,
register-transfer level systems)
• knowledge of design methodologies for each of the previous classes, the approach being oriented to automated synthesis
• acquaintance with a Hardware Description Language and ability to describe designed hardware resorting to it
• skills to use CAD tools for description, simulation and synthesis.
In this context, the course aims to provide adequate knowledge of hardware and hardware design methodologies, ranging from combinational circuits, to sequential circuits, Finite State Machines and register-transfer level systems. VHDL is the Hardware Description Language used, whereas Verilog is introduced by difference. The emphasis is not on the syntax of the language, rather on hardware design. Constructs and features of the language are introduced whenever they serve the purpose of illustrating new concepts in the hardware. The teaching methodology is thus not language-oriented, rather design-oriented. The development of a sound and structured hardware design methodology is one of the core goals of the Course. The course completes the design methodologies acquired in previous basic digital design courses and extends them to the register-transfer level, where the FSM-D model is adopted (Finite State Machine with Datapath) to overcome the limits of the classical FSM when bigger systems are considered, where operations and control coexist. The free Xilinx design toolkit Vivado HL WebPACK Edition is used to describe, simulate and synthesize complex systems in a lab-based hands-on experience. As simulation-based verification can’t be exhaustive in real-world designs, verification techniques based on formal methods, in particular combinational and sequential equivalence check and model checking, are introduced.

• Knowledge of the syntax and semantics of VHDL
• Ability to describe complex digital systems in VHDL at various levels of abstraction
• Basic knowledge of the Verilog language by difference w.r.t. VHDL
• Knowledge of the fundamental features of embedded systems
• Knowledge of the metrics to evaluate designs
• Knowledge of the design methodologies for register-transfer level systems
• Ability to design complex digital systems at the register-transfer level with CAD tools
• Ability to verify by simulation complex digital system designs
• Knowledge of the main formal verification techniques with particular emphasis on combinational and sequential equivalence check and model checking

As outcomes of the Course, students will acquire:
• in terms of knowledge:
- model and operation of combinational and sequential circuits, libraries of popular combinational and sequential
blocks, Finite State Machines, register-transfer level systems
- structured methodologies to design hardware, with particular emphasis on register-transfer level design
- the syntax and semantics of VHDL
- Verilog by difference w.r.t. VHDL
- basic notions on evaluation metrics for embedded systems
- basic notions on formal verification for combinational circuits and Finite State Machines based on symbolic
techniques and Model Checking
• in terms of skills:
- the ability to describe complex digital systems in VHDL and Verilog at various levels of abstraction
- the ability to simulate and synthesize complex digital system by means of a state-of-the-art CAD toolkit
• in terms of competences:
- the use of knowledge, skills and methodologies for the design of complex hardware systems
- the improvement of the autonomy of judgment thanks to the problem-solving oriented design activity, that
requires to understand the specifications of the problem and to complete them, as well as to explore several
alternatives
- improvement of communication skills thanks to reports required for the mini-assignment and for the lab
sessions.

Knowledge of basic design techniques for combinational and synchronous sequential circuits.

Knowledge of:
• Boolean Algebra
• basic design techniques for combinational and synchronous sequential circuits.
Attitude towards:
• problem solving, as an activity with "design and creative" characteristics. It differs from mainly executive tasks, limited to the use of tools and / or techniques learned. Therefore, the skills of inductive and deductive reasoning, logic and conceptualization of abstract problem models must be considered as prerequisites for an effective approach to this Course.

• VHDL: structure of VHDL files: entity/architecture; description styles: behavioral, dataflow, structural; lexical elements; objects: signals, variables and constants; data types: scalar types, composite types; operators and attributes; concurrent statements: concurrent signal assignments, generate statements, concurrent processes, component instantiations; sequential statements: processes, conditional statements, iterative statements; partitioning techniques: blocks, packages, libraries, components, configurations. Examples of combinational, synchronous and basic register-transfer level designs in VHDL.
• Register Transfer-level embedded systems design: design metrics and their optimization; key technologies for embedded systems: processor technology, IC technology, design technology; single-purpose processor design: High-Level State Machines, the FSM-D model, from the algorithm to the FSM-D, synthesis of the datapath, synthesis of the control unit, description in VHDL; optimization of single-purpose processors: algorithm, FSM-D, datapath, FSM; optimization of Finite State Machines (FSMs): state minimization (simplified and exact equivalent state detection algorithm), state encoding heuristics.
• Formal verification: approaches to design verification: simulation vs. formal verification; theorem proving: propositional logic, first-order logic, higher-order logic; equivalence checking: Binary Decision Diagrams, combinational equivalence check, sequential equivalence check (symbolic reachability analysis, the product machine model); Model Checking: linear-time temporal logic, branching-time temporal logic, liveness and safety properties, model checking algorithms.
• Verilog by difference w.r.t. VHDL: descriptions of combinational circuits, sequential circuits and RTL designs.

• Basic Hardware (integrated with design methodologies and VHDL) (20h):
- Combinational circuits
- Sequential circuits
- Combinational blocks
- Sequential blocks
- Finiste State Machines.
• VHDL:
- structure of VHDL files: entity/architecture;
- description styles: behavioral, dataflow, structural;
- lexical elements;
- objects: signals, variables and constants;
- data types: scalar types, composite types;
- operators and attributes;
- concurrent statements: concurrent signal assignments, generate statements, concurrent processes,
component instantiations;
- sequential statements: processes, conditional statements, iterative statements;
- partitioning techniques: blocks, packages, libraries, components, configurations.
• register transfer level embedded systems design (20h):
- design metrics and their optimization;
- key technologies for embedded systems: processor technology, IC technology, design technology;
- single-purpose processor design: High-Level State Machines, the FSM-D model, from algorithm to FSM-D,
synthesis of the datapath, synthesis of the control unit, description in VHDL;
- optimization of single-purpose processors: algorithm, FSM-D, datapath, FSM;
- optimization of Finite State Machines: state minimization (simplified and exact equivalent state detection
algorithm), state encoding heuristics.
• formal verification (10h):
- approaches to design verification: simulation vs. formal verification;
- theorem proving: propositional logic, first-order logic, higher-order logic;
- equivalence checking: Binary Decision Diagrams, combinational equivalence check, sequential equivalence check
(symbolic reachability analysis, the product machine model);
- Model Checking: linear-time temporal logic, branching-time temporal logic, liveness and safety properties,
model checking algorithms.
• Verilog by difference w.r.t. VHDL (10h):
- descriptions of combinational circuits, sequential circuits and RTL designs.

Lectures (40h) covering the syllabus + 20h lab work: students work with the Xilinx® Vivado HLS package to develop RT-level designs according to the methodologies described in the lectures.
An optional short assignment is available. It is an individual project, assigned mid-December, to be handed in for evaluation before the oral exam and no later than the end of February exam session. It entails max 2/30 bonus on the final mark.

Lectures (40h) covering the syllabus + 20h lab work: students work with the Xilinx® Vivado HLx Editions package to develop RT-level designs according to the methodologies described in the lectures. Prerecorded lectures are available on the website. Lab sessions consist of a mix of prerecorded tutoring and student/teacher interaction via VirtualClassroom. As the Xilinx® Vivado HLx Editions package is freely available for students and may be installed on any laptop, physical presence in a lab is not necessary.
An optional short assignment is available. It is an individual project, assigned mid-December, to be handed in for evaluation before the oral exam and no later than the end of February exam session. It entails max 2/30 bonus on the final mark.

Handouts published on the course site.
Additional readings:
• F. Vahid, “Digital Design with RTL design, VHDL and Verilog”, 2nd edition, John Wiley, 2010
• D. Pellerin, D. Taylor “VHDL Made easy!”, Prentice Hall 1997
• F. Vahid, T. Givargis “Embedded System Design: a unified hardware/software introduction”, John Wiley, 2002
• M.Ercegovac, T. Lang, J. Moreno “Introduction to digital systems”, John Wiley, 1999
•

Handouts published on the course site.
Additional readings:
• F. Vahid, “Digital Design with RTL design, VHDL and Verilog”, 2nd edition, John Wiley, 2010
• D. Pellerin, D. Taylor “VHDL Made easy!”, Prentice Hall 1997
• F. Vahid, T. Givargis “Embedded System Design: a unified hardware/software introduction”, John Wiley, 2002
• M.Ercegovac, T. Lang, J. Moreno “Introduction to digital systems”, John Wiley, 1999

The exam consists in a written and in an oral part.
Written exam (max 150 minutes): designs on paper of combinational networks, Finite State Machines and RT-level complex systems described in VHDL. Number of exercises varies according to difficulty. No books, slides or any other material allowed, except a VHDL primer. The goal of the written part is to ascertain that the student has acquired the ability to design complex digital systems and to describe them in VHDL at various levels of abstraction. Evaluation criteria: understanding of specifications, functional completeness of solution, correctness of VHDL code. No later than 3 days after the written exam, the student has to upload a simulable VHDL file and its testbench, as well as a short report focusing on the design choices and on the differences between the version handed in at the written exam and the uploaded one. If the VHDL files are uploaded before the deadline, the written exam is corrected and ranked. If the mark is sufficient (>= 15), follows a mandatory oral exam on all the topics dealt with during the course. Questions concern knowledge (definitions, concepts, etc.) and short exercises (in particular related to formal verification and Verilog).
The oral exam aims at ascertaining that the student has acquired the notions in Formal Verification and Verilog that are part of the course syllabus. The final mark takes into account the results both in the written and the oral parts as a whole and not as an average. An optional short assignment is available. It is an individual project, assigned mid-December, to be handed in for evaluation before the oral exam and no later than the end of February exam session. It entails max 2/30 bonus on the final mark.

Gli studenti e le studentesse con disabilità o con Disturbi Specifici di Apprendimento (DSA), oltre alla segnalazione tramite procedura informatizzata, sono invitati a comunicare anche direttamente al/la docente titolare dell'insegnamento, con un preavviso non inferiore ad una settimana dall'avvio della sessione d'esame, gli strumenti compensativi concordati con l'Unità Special Needs, al fine di permettere al/la docente la declinazione più idonea in riferimento alla specifica tipologia di esame.

The exam consists in a written and in an oral part.
Written exam (max 150 minutes): designs on paper of combinational networks, Finite State Machines and RT-level complex systems described in VHDL. Number of exercises varies according to difficulty. No books, slides or any other material allowed, except a VHDL primer. The goal of the written part is to ascertain that the student has acquired the ability to design complex digital systems and to describe them in VHDL at various levels of abstraction. Evaluation criteria: understanding of specifications, functional completeness of solution, correctness of VHDL code. No later than 3 days after the written exam, the student has to upload a simulable VHDL file and its testbench, as well as a short report focusing on the design choices and on the differences between the version handed in at the written exam and the uploaded one. If the VHDL files are uploaded before the deadline, the written exam is corrected and ranked. If the mark is sufficient (>= 15), follows a mandatory oral exam on all the topics dealt with during the course. Questions concern knowledge (definitions, concepts, etc.) and short exercises (in particular related to formal verification and Verilog).
The oral exam aims at ascertaining that the student has acquired the notions in Formal Verification and Verilog that are part of the course syllabus. The final mark takes into account the results both in the written and the oral parts as a whole and not as an average. An optional short assignment is available. It is an individual project, assigned mid-December, to be handed in for evaluation before the oral exam and no later than the end of February exam session. It entails max 2/30 bonus on the final mark.

In addition to the message sent by the online system, students with disabilities or Specific Learning Disorders (SLD) are invited to directly inform the professor in charge of the course about the special arrangements for the exam that have been agreed with the Special Needs Unit. The professor has to be informed at least one week before the beginning of the examination session in order to provide students with the most suitable arrangements for each specific type of exam.

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Corso Duca degli Abruzzi, 24 - 10129 Torino, ITALY

Corso Duca degli Abruzzi, 24 - 10129 Torino, ITALY