en
Politecnico di Torino
Anno Accademico 2014/15
01QSCIU
Reconfigurable computing
Dottorato di ricerca in Ingegneria Informatica E Dei Sistemi - Torino
Docente Qualifica Settore Lez Es Lab Tut Anni incarico
Sterpone Luca ORARIO RICEVIMENTO O2 IINF-05/A 20 0 0 0 10
SSD CFU Attivita' formative Ambiti disciplinari
*** N/A ***    
Obiettivi dell'insegnamento
IL CORSO SI TERRA' NEL PERIODO: FEBBRAIO - MARZO 2015


L’obiettivo del corso è l’introduzione al paradigma della computazione riconfigurabile, oggi praticabile grazie alla potenzialità dei dispositivi elettronici esistenti quali dispositivi logici programmabili (FPGA e CPLD), multicore e sistemi integrati su chip programmabili. La computazione riconfigurabile trova applicazione in diversi contesti quali le telecomunicazioni, l’aerospazio, la biomedica e l’automotive nonché per l’accelerazione di calcoli per applicazioni matematiche e scientifiche. Nel corso saranno presentate teorie e metodi, tecniche di progetto e applicazioni scientifiche basate sul paradigma della computazione riconfigurabile. Le lezioni saranno supportate anche dall’analisi dei principali articoli di ricerca presentati sulla tematiche.

The goal of the course is the introduction of the reconfigurable computing paradigm, existing today thanks to the capabilities of electronic devices such as logic programmable devices (FPGAs and CPDs), Multicores and Systems on Programmable Chips (SoPC). The reconfigurable computing is applied to several contest such as telecommunication, aerospace, automotive, biomedical and automotive as well as for the speed-up of scientific and mathematical applications. During the course, theories and methods, design techniques and scientific applications based on the reconfigurable computing paradigm will be presented. Lectures will be supported also with the principal research papers related on the topics.
Programma
Introduction on reconfigurability. Logic Programmable Devices. Field Programmable Gate Arrays. Dynamic Reconfigurability. Partial and Dynamic reconfiguration. Reconfigurable Placement. Reconfigurable Routing. Network virtualization with FPGAs. On-chip monitoring infrastructures. Dynamically reconfigurable Circuits. Multicore Programmable Devices. Logic Emulation. Fault Simulation. Reconfigurable Coprocessors. Reconfigurable Memory Security. Reconfigurability for aerospace. Automotive reconfigurable platforms. Biomedical reconfigurable applications. Safety reconfigurable computing. Fast mathematic transformation based on reconfigurable computing.


Duration: 20 hours (4 credits, with final discussion/verification)

* When and where:
TU Mar. 03, 2015, 10.00am to 01.00pm, classroom C
TU Mar. 10, 2015, 10.00am to 12.00pm, classroom C
TU Mar. 17, 2015, 10.00am to 12.00pm, classroom C
TH Mar. 19, 2015, 09.30am to 01.30pm, classroom C
TU Mar. 24, 2015, 10.00am to 12.00pm, classroom C
TH Mar. 26, 2015, 10.00am to 12.00pm, classroom C
TU Mar. 31, 2015, 10.00am to 12.00pm, classroom C
TH Apr. 02, 2015, 10.00am to 01.00pm, classroom C

* Exam: written examination and/or possible individual project/presentation.
Orario delle lezioni
Statistiche superamento esami

Programma provvisorio per l'A.A.2014/15
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