The usage of electronic systems in applications where failures may results in critical consequences (e.g., in space, aircrafts, automobiles, trains, biomedical equipment) requires ensuring that the probability of a failure does not overcome some maximum threshold. This can be achieved by identifying and removing defective products (test) and by making products resilient to faults (fault tolerance). The course introduces methods and techniques for the design of reliable electronic circuits and systems, with special emphasis on the test performed to identify products affected by hardware faults, and on the solutions to harden electronic products with respect to faults and to the techniques to estimate the probability that possible faults may force them to produce failures.

- Knowledge of the concepts of testing and dependability. - Knowledge of the main techniques used for testing a digital circuit. - Knowledge of the main techniques used for testing an embedded system. - Knowledge of the basic techniques used for hardening an electronic products with respect to possible faults. - Knowledge of the main techniques for estimating the reliability of an electronic system. - Capability of developing the test plan for a digital device or embedded system - Capability to use the main software tools for testing an embedded system: fault simulators, automatic test pattern generators, automatic scan chain inserters. - Knowledge of the concept of Built-In Self-Test (BIST) and Boundary Scan (BS). - Knowledge of the concept of Failure Mode and Effect Analysis (FMEA). - Capability of designing BIST hardware modules.

The course is better followed if the student owns the knowledge about • Digital system design • Microelectronics.

1. Introduction to test and dependability (1 credit) a. Dependability: definition, attributes b. Fault models (temporary and transient): stuck-at, bridge, open, delay, SEU, SET c. Test of ICs, boards and systems d. Defect level: definition and evaluation e. ATEs 2. Techniques and tools for generating test stimuli for combinational and sequential modules (1 credit) a. Fault simulation b. Automatic Test Pattern Generation 3. Techniques and tools for testing specific modules (1 credit) a. Memory test b. Processor test 4. Design for Testability techniques (1 credit) a. Scan b. BIST c. Boundary Scan d. System on Chip test (IEEE 1500 and 1687) 5. Board test (0.5 credit) a. Main steps in PCB test b. IEEE 1149.1 6. Basics in fault tolerant system design (1.5 credits) a. Basic fault tolerant design solutions (hw redundancy, information redundancy, time redundancy) b. Reliability evaluation (FMEA, radiation experiments, fault injection)

Laboratory activities are an integral part of this course. During the lab sessions students will face the practical aspects introduced by lectures. Lab sessions will allow students to work with commercial tools for Fault Simulation, Scan Insertion and Automatic Test Pattern Generation. Students will also be asked to develop assignments concerning the course subjects.

Students may benefit of the following textbook: M. Bushnell, V. Agrawal: Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits Kluwer Academic Publisher, 2000 Slides will be provided to students registered to the course through the Student Teaching Portal, as well as any additional non-copyrighted information material that will be used in the course.

Modalità di esame: Prova scritta (in aula); Prova orale facoltativa; Progetto di gruppo;

Exam: Written test; Optional oral exam; Group project;

... The exam will be based on a written part in which the students will be asked to answer to some (about 5) questions and exercises. Each exercise can contribute with up to 6 points to the final score. The exam will last for about 90 minutes. Students cannot access any material during the exam. If the student achieves at least 18 points in the written exam, he/she may ask for an oral exam. During the oral exam the student will be asked to reports about issues and solutions described during the course, or solve specific problems related to the course topics. The oral exam is organized in about 3 questions and can increase or decrease the score achieved with the written exam. The students will be allowed to work on an assignment (typically, in groups of 2 people) which could increase the score of the written exam by 0 to 5 points.

Gli studenti e le studentesse con disabilità o con Disturbi Specifici di Apprendimento (DSA), oltre alla segnalazione tramite procedura informatizzata, sono invitati a comunicare anche direttamente al/la docente titolare dell'insegnamento, con un preavviso non inferiore ad una settimana dall'avvio della sessione d'esame, gli strumenti compensativi concordati con l'Unità Special Needs, al fine di permettere al/la docente la declinazione più idonea in riferimento alla specifica tipologia di esame.