PORTALE DELLA DIDATTICA

PORTALE DELLA DIDATTICA

PORTALE DELLA DIDATTICA

Elenco notifiche



Nano & Quantum Computing

01SHORV

A.A. 2018/19

Course Language

Inglese

Degree programme(s)

Doctorate Research in Ingegneria Elettrica, Elettronica E Delle Comunicazioni - Torino

Course structure
Teaching Hours
Lezioni 40
Lecturers
Teacher Status SSD h.Les h.Ex h.Lab h.Tut Years teaching
Graziano Mariagrazia Professore Associato IINF-01/A 28 0 0 0 3
Co-lectures
Espandi

Context
SSD CFU Activities Area context
*** N/A ***    
2018/19
PERIOD: FEBRUARY - MARCH This course aims at giving the student a detailed overview of the computation circuits and systems for computations that are expected to become the main actor in the forthcoming scenario, going beyonf the ultra-scaled CMOS technologies and focusing the attention on the emerging technologies among which the winner is still to be defined. Those devices, circuits and systems will be analyzed considering the connection among CMOS and beyond COMS devices with circuits and architectures based on them. This because the complexity of nanoscale systems does not allow to disentangle different planes as design, analysis and evaluation.
PERIOD: FEBRUARY - MARCH This course aims at giving the student a detailed overview of the computation circuits and systems for computations that are expected to become the main actor in the forthcoming scenario, going beyonf the ultra-scaled CMOS technologies and focusing the attention on the emerging technologies among which the winner is still to be defined. Those devices, circuits and systems will be analyzed considering the connection among CMOS and beyond COMS devices with circuits and architectures based on them. This because the complexity of nanoscale systems does not allow to disentangle different planes as design, analysis and evaluation.
• State of the art: nanocomputing in ULTRA scaled CMOS: ◦ CMOS scaling trends at device levels: scaling, leakage, double-gate transistors, FinFET, … ◦ Circuit and architectural techniques: dark silicon, dynamic voltage scaling, subthreshold computation, ..... • Field coupled nanocomputing (FCN): ◦ quantum dot cellular automata (QCA), nano magnetic logic (NML), molecular QCA, silicon based QCA; discussions on technology, behavior, models, energyconsumption, speed, area ◦ interconnections: magnetic domain walls, spin waves, molecular wires ◦ designing a FCN circuit: a new design paradigm toward intrinsic pipelining ◦ circuits and architectures based on FCN structures: syncrhonous, asynchronous, null-convention logic; how to solve feedback problems; cut set retiming; solutions based on systolic arrays and interleaving • Nanoarray nanocomputing based on nanowires: ◦ devices: Gate-All-Around transistors, Ambipolar transistors (silicon based, zinc-oxide, carbon nanotubes, …) ◦ circuits: nano-PLA, NanoASIC, reconfigurable nanoFPGA ◦ architectures: sea of nanoarrays for massive computation and "embarassingly parallel" elaboration • Logic in memory ◦ Devices: resistive memories, memristors, nanomagnets and magnetic memories ◦ Circuits: logic embedded in memory, communications and protocols ◦ Architectures: caches to the limit, use hic what you need nunc, search nearby what you need later • Devices and architectures for quantum computation ◦ Fundamentals of quantum computation ◦ Devices and technologies for quantum computation ◦ Circuits and architectures
• State of the art: nanocomputing in ULTRA scaled CMOS: ◦ CMOS scaling trends at device levels: scaling, leakage, double-gate transistors, FinFET, … ◦ Circuit and architectural techniques: dark silicon, dynamic voltage scaling, subthreshold computation, ..... • Field coupled nanocomputing (FCN): ◦ quantum dot cellular automata (QCA), nano magnetic logic (NML), molecular QCA, silicon based QCA; discussions on technology, behavior, models, energyconsumption, speed, area ◦ interconnections: magnetic domain walls, spin waves, molecular wires ◦ designing a FCN circuit: a new design paradigm toward intrinsic pipelining ◦ circuits and architectures based on FCN structures: syncrhonous, asynchronous, null-convention logic; how to solve feedback problems; cut set retiming; solutions based on systolic arrays and interleaving • Nanoarray nanocomputing based on nanowires: ◦ devices: Gate-All-Around transistors, Ambipolar transistors (silicon based, zinc-oxide, carbon nanotubes, …) ◦ circuits: nano-PLA, NanoASIC, reconfigurable nanoFPGA ◦ architectures: sea of nanoarrays for massive computation and "embarassingly parallel" elaboration • Logic in memory ◦ Devices: resistive memories, memristors, nanomagnets and magnetic memories ◦ Circuits: logic embedded in memory, communications and protocols ◦ Architectures: caches to the limit, use hic what you need nunc, search nearby what you need later • Devices and architectures for quantum computation ◦ Fundamentals of quantum computation ◦ Devices and technologies for quantum computation ◦ Circuits and architectures
Modalità di esame:
Exam:
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Gli studenti e le studentesse con disabilità o con Disturbi Specifici di Apprendimento (DSA), oltre alla segnalazione tramite procedura informatizzata, sono invitati a comunicare anche direttamente al/la docente titolare dell'insegnamento, con un preavviso non inferiore ad una settimana dall'avvio della sessione d'esame, gli strumenti compensativi concordati con l'Unità Special Needs, al fine di permettere al/la docente la declinazione più idonea in riferimento alla specifica tipologia di esame.
Exam:
In addition to the message sent by the online system, students with disabilities or Specific Learning Disorders (SLD) are invited to directly inform the professor in charge of the course about the special arrangements for the exam that have been agreed with the Special Needs Unit. The professor has to be informed at least one week before the beginning of the examination session in order to provide students with the most suitable arrangements for each specific type of exam.
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