The course is optional in the BS-level programme in Electronic And Communications Engineering and is offered in the second period of the third year. It deals with the basics of Digital Electronics, covering all different aspects of digital design. The most important design methodologies related to basic digital circuits up to complex processing systems are shown and applied. The knowledges and the abilities developed in this module are necessary for the more advanced courses on digital systems

-Knowledge of basic combinatorial circuits and their synthesis tools; -Knowledge of sequential circuits and their synthesis tools; -Knowledge and ability in the use of a Hardware Description Language such as VHDL: description and syntesis of digital blocks. -Knowledge of complex programming digital circuits (FPGAs); -Knowledge of memory structures and architectures, and their use in processing systems.

Boole's Algebra; elementary combinatorial and sequential digital functions; concept of finite state machine.

- Combinatorial circuits: synthesis techinques for basic and arithmetic circuits (1 CFU) - Sequential circuits: elementary FSMs and complex control architectures (ASM charts) (2 CFU) - Hardware Description Languages (VHDL): statements, data structures and coding techniques for hardware description and modelling (2 CFU); - Memories: circuits, architectures and applications (1 CFU);

Practice classes will focus on small digital designs. Laboratory sessions consist in the development, synthesis and implementation of digital designs, described using VHDL language. Evaluation boards will be available to test the designs. Overall, seven laboratory assignments will be completed by groups of 3 or 4 students. A report is required for each laboratory session and it will be considered in the final grade. Assignments must be completed and delivered within specific dates distributed during the spring term.

The learning material used for the lessons is made available through the course website. This includes notes provided by the professor, datasheets of electronic components, free ebooks and past written tests. Reference books: "Fundamentals of Digital Logic with VHDL Design (Third Edition)" di Stephen Brown e Zvonko Vranesic , Mc Graw Hill

Modalità di esame: Prova scritta (in aula); Prova orale obbligatoria; Progetto di gruppo;

Exam: Written test; Compulsory oral exam; Group project;

... The written test includes three open answer questions and one design problem. The available time is 2 hours. The questions cover all course topics and they intend to verify the acquired knowledge and capabilities. The design problem requires to understand the initial specifications, to develop a detailed datapath architecture, to properly model the control unit, and to describe one or multiple elements by means of VHDL. No books and notes are admitted. Normally, the same weight is given to each question. However, the weight of questions that achieved a very low average mark may be slightly reduced. A mark at least equal to 18/30 is required to pass to the oral exam, which concerns both the subjects already covered in the written test and the discussion of the submitted projects. Normally, two questions are asked and one of them is about laboratory projects. The evaluation of laboratory projects is based on: - completeness, - adopted methodology - obtained results. The final grade is a weighted average of the written and oral exams (weighted 0.8) and lab reports (weighted 0.2).

Gli studenti e le studentesse con disabilità o con Disturbi Specifici di Apprendimento (DSA), oltre alla segnalazione tramite procedura informatizzata, sono invitati a comunicare anche direttamente al/la docente titolare dell'insegnamento, con un preavviso non inferiore ad una settimana dall'avvio della sessione d'esame, gli strumenti compensativi concordati con l'Unità Special Needs, al fine di permettere al/la docente la declinazione più idonea in riferimento alla specifica tipologia di esame.