The course is taught in English. The course is compulsory (in alternative with Sistemi Digitali Integrati) for the Master Program and is at the 1st semester of the 1st year. The goal is to provide a deep insight into design methodologies of complex digital systems. This task requires a clear view of the possible design choices and the ability to integrate different components. The course will analyze systems composed of microprocessors/microcontrollers, programmable logic, memories and interfaces to the external world. Special emphasis will be given to how to interface, program, interconnect digital blocks and to the "design flow", namely to design tools and methodologies.

• Knowledge of the general structure of a digital processing system: processing element, memory. I/O, interconnection network and timing. • Knowledge of the main characteristics of general purpose microprocessors: internal structure, taxonomy, programming model. • Ability to integrate additional functions into a processing unit and to interface a coprocessor to a general purpose processor. • Knowledge of existing memory types. Taxonomy, access protocols, physical models, interfacing and choice according to cost, area and performance parameters. • Knowledge of memory hierarchy in a processing system: cache and virtual memory. • Knowledge of the main peripheral devices: Digital and analog I/O, synchronous and asynchronous communication systems. Buffering strategies and clocking schemes, interfacing and implementation methodologies. • Ability to integrate custom peripherals into existing processing units. • Knowledge of the use of programmable logic components (PLD, FPGA) in embedded systems: design flow, area and speed optimization. • Knowledge of interconnection technologies at the physical level: technologies, transmission lines, crosstalk, basics of electromagnetic compatibility. • Knowledge of interconnection technologies at the logical level: topologies, addressing, error handling, examples of standards. • Knowledge of the techniques for the generation and distribution of timing signals. • Knowledge of the techniques for analyzing specification and constraints in complex digital systems. • Ability to understand specifications and requirement in the design of complex digital systems. Analysis of algorithmic choices (based on computational complexity, interconnection bandwidth, data representation both format and bit-width). • Knowledge of standard techniques to design control units in complex digital systems. • Knowledge of standard techniques to design an execution unit either in parallel or sequential form.

Basic knowledge and capability to operate on the following topics are required: • Elementary combinatorial and sequential logic elements • Finite State Machines ; • Elementary Arithmetic Circuits; • Memories (structure and architecture); • Computer architecture elements; • C language Programming; • Hardware description languages (VHDL/Verilog); • Basic knowledge of FPGA use and programming.

The course may be approximately divided into 4 main parts: 1. Computer architectures for embedded systems (3 CFU) a. Microprocessor Architecture b. Peripheral interfacing, DMA and interrupts c. Programmable devices 2. Memory structures (3 CFU) a. Memory technology b. Volatile and non-volatile memory structures c. Cache memories 3. Interconnection and interfacing structures (2 CFU) a. Signal propagation, delay and skew b. Synchronous and asynchronous transfer cycles c. Transactions, Arbitration and Addressing d. Parallel communication structures, bus e. Serial communication structures. Peripheral buses 4. Integrated processing systems (2 CFU) a. Specification and requirements analysis b. Timing analysis in complex digital systems c. Control units and execution units

The course is structured in classes and laboratories. During classes theoretical aspects are discussed together with examples and execises. The laboratories (in general 6) are based on the use of programmable FPGA devices for the implementation of embedded systems including processors and standard or custom peripherals designed by the students. Laboratory activities require both the design of hardware parts and the writing of software modules. Each laboratory work is developed by a team (3-4 students) and corresponds to a simple design. A written report within a time limit of one week is also required. The final evaluation of the laboratory work is the average of the evaluations of the individual laboratories, is common to all the students of each team/group and has a maximum value of 5/30.

The book "Embedded system design" di F. Vahid covers approximately 30% of the course. Slides of the course together with manuals and datasheets of the components analyzed during classes are available. Moreover, all laboratory assignments and material are available as well. All the material is available on "Portale della Didattica".

Modalità di esame: Prova scritta (in aula); Prova orale obbligatoria; Prova pratica di laboratorio; Progetto di gruppo;

Exam: Written test; Compulsory oral exam; Practical lab skills test; Group project;

... The verification of the learning will take place through the laboratory work evaluation (optional, but strongly recommended), a written exam (mandatory) and an oral exam (mandatory). The written exam has a duration of approximately 2 hours and is composed of 2 design-based exercises. Books, notes or any other kind of material is not allowed during the exam. Students are allowed to take the oral exam if the written exam is rated at least as “sufficient”. The oral exam is made of questions on the theoretical or the descriptive parts of the course as well as on laboratory-related aspects. The total exam score is a weighted average of the written and oral exam scores plus the laboratory score. Special projects are available for strongly motivated students. A special project leads to at most a +3 to the final score.

Gli studenti e le studentesse con disabilità o con Disturbi Specifici di Apprendimento (DSA), oltre alla segnalazione tramite procedura informatizzata, sono invitati a comunicare anche direttamente al/la docente titolare dell'insegnamento, con un preavviso non inferiore ad una settimana dall'avvio della sessione d'esame, gli strumenti compensativi concordati con l'Unità Special Needs, al fine di permettere al/la docente la declinazione più idonea in riferimento alla specifica tipologia di esame.