The course is taught in English. This course introduces the main mathematical models and methods used for the synthesis and verification of embedded hardware and software. It assumes a good knowledge of digital hardware design (with VHDL or Verilog) and of software implementation (with C, C++ or Java) for embedded systems, including a basic knowledge of real-time operating systems. It provides the ability to select and use the best tools and methods for hardware/software co-design, as well as simulation and performance analysis. It provides knowledge about the SystemC language, synchronous languages and dataflow networks.

• Knowledge of the main formal models and specification languages based on extended finite state machines and dataflow networks. • Knowledge of the hardware and software synthesis methods for synchronous languages and dataflow networks. • Knowledge of embedded software performance analysis techniques. • Ability to analyze at a high level the computational and communication requirements of an embedded application. • Ability to select the best specification languages and implementation tools, and to select a hardware/software architecture for an embedded system. • Ability to create a simulation model of an embedded system using a modeling language (e.g. SystemC).

• Digital hardware design using Verilog or VHDL • C, C++ or Java programming • Architecture of at least one CPU, memory architecture and micro-controller. • Micro-controller peripheral programming. • Elements of real-time schedulability theory.

Topics (about 1/2 credit each): • Characteristics of embedded systems, architectures and design flows. • Control-dominated systems and data-dominated systems. • SystemC language: syntax and semantics. Usage examples. • SystemC design at Transaction level (TLM) and Register Transfer Level (RTL). • Dataflow networks: Kahn Process Networks, determinacy and schedulability. Usage examples. • Static scheduling of dataflow networks, minimizing code size or data memory size. • Hardware synthesis of dataflow networks. • Extended Finite State machines. Synchronous Moore and Mealy composition. • Synchronous languages: StateCharts, Esterel and ECL. Control constructs (emit, await, abort, parallel). Usage examples. • Hardware and software synthesis techniques for Esterel. Interfacing methods with operating systems and peripherals. • Formal property verification (liveness and safety) using synchronous languages. • Worst-Case Execution Time analysis for software via simulation and formal methods.

Discussion sessions will reinforce concepts described during lessons and apply them to the solution of simple exercises, to be first solved individually and then discussed at the blackboard. Laboratory sessions will require the use of the SystemC language to model the functionality and performance of an embedded system, including both control-dominated and data-dominated aspects. Other laboratory sessions will teach the basics of high-level synthesis tool usage.

Peter Marwedel, “Embedded System Design”, Kluwer Academic Publishers, 2003. Maurizio Tranchero, Luciano Lavagno et al., “Modeling and Optimization of Embedded Systems”, available on “portale della didattica”. Slides used during lessons and laboratory guides, also available on “portale della didattica”.

Modalità di esame: Prova orale facoltativa; Prova scritta tramite PC con l'utilizzo della piattaforma di ateneo;

The final exam is composed of a written and an optional oral part. The written test, which is carried out on line using the Exam/Respondus platform, includes both numerical exercises and multiple choice questions about the main topics of the course (SystemC, ECL, dataflow networks, worst case execution time analysis). It lasts 1.5-2 hours. Neither books nor notes can be used. The maximum score is 30. Examples of written tests from past years are posted on "portale della didattica". The oral exam, which is carried out using the Virtual Classroom, can be requested by the student after seeing the graded written test, lasts for 15-20 minutes, and covers all the course topics. The final grade is a weighted average of the written and oral exam results, and can be 30 e lode after a very successful oral exam.

Modalità di esame: Prova scritta (in aula); Prova orale facoltativa; Prova scritta tramite PC con l'utilizzo della piattaforma di ateneo;

The final exam is composed of a written and an optional oral part. The written test, which is carried out on line using the Exam/Respondus platform on-site or remotely, includes both numerical exercises and multiple choice questions about the main topics of the course (SystemC, ECL, dataflow networks, worst case execution time analysis). It lasts 1.5-2 hours. Neither books nor notes can be used. The maximum score is 30. Examples of written tests from past years are posted on "portale della didattica". The oral exam, which is carried out either in person or using the Virtual Classroom, can be requested by the student after seeing the graded written test, lasts for 15-20 minutes, and covers all the course topics. The final grade is a weighted average of the written and oral exam results, and can be 30 e lode after a very successful oral exam.