The course is taught in English. This is a mandatory course (in some curricula it can be replaced by “Elettronica Analogica e di Potenza”, in Italian) for the Master Degree in Electronics. The course aim is to review and study in depth various subjects of Analog Electronics, with an emphasis on contents related with telecommunication applications. The most relevant issues related with analog and telecommunication subsystems are analysed in detail, to establish a reference point for the following courses, which addresses more specific subjects.

- Knowledge of the various types of mixers and amplifier stages and their applications; ability to analyze and design the related circuits, carrying out device selection and evaluating the various design choices. - Ability to analyse and design amplifiers and other circuits based on Operational Amplifiers; knowledge and application of parameters and selection criteria for integrate Op Amps and other integrated complex functional units. - Quantitative evaluation of effects of sampling and quantization in Analog to Digital conversion; design of A/D systems with error budget allocation. Knowledge of parameters and circuits for A/D and D/A converters. Ability to select active and passive device, and to integrate them in a complex design. Knowledge of differential converters, with evaluation of oversampling and noise shaping effects. - Knowledge of radio systems architecture for receivers and transmitters, including ZIF digital architectures and SW radio (SDR). Operation, parameters and basic circuit for radio systems units. Ability to define the characteristics and to design some of these functional units. - Knowledge of behaviour, models, and applications of Phase Lock Loops (PLLs); ability to analyze a PLL systems, select integrated devices and design circuits for PLLs functional units and for simple PLL-based applications.

Knowledge of basic electronics, ability to analyze electric networks and circuits. Knowledge of linear and large signal models of MOS and BJTs, and ability to use these models in basic amplifier circuits. Models of real Operational Amplifiers, circuits with negative and positive feedback, ability to design amplifiers in basic configurations. Knowledge and design of most used functional units, such as filters, voltage regulators, signal generators.

Radio systems. Heterodyne receivers and transmitters, ZIF (2 CFU) - Basic architectures for receiving and transmitting radio systems; heterodyne architecture - Image signals, I/Q mixer, image rejection techniques; - Digital radio systems, SDR ; - Basic modules : LNA, PA, mixer, oscillators; intermodulation and IPs. Review of amplifier stages, amplifier and filter circuits, (including SC); operating limits (2.5 CFU) - basic amplifier stages; nonlinearity, distortion, harmonics, gain compression - tuned amplifier, large signal analysis - sine signal generators - review of time-continuos filters - basic SC circuits; parameters and nonidealities, - amplifiers and filters with SC circuits. Phase lock loops (PLL) (2 CFU) - PLL linear analysis. Loop filter, phase error, capture and lock ranges - Phase detector and VCO circuits - PPL synthesizers and direct digital synthesizers (DDS) - Examples of integrated PLL and ADPLL - Applications for synchronous demodulation of analog and digital signals, and clock re-synchronization. A/D/A conversion, parameters, errors, ADC and DAC circuits (2.5 CFU) - Review of analog and digital signal parameters, sampling, aliasing, SNRq; - Parameters and errors in DAC and ADC, taxonomy based on complexity and speed; residue and pipeline circuits. - Differential converters (delta and sigma-delta), oversampling and noise shaping; decimation and interpolation filters; - Nonlinear converters, logarithmic circuits, voice signal encoding techniques; - Signal conditioning, anti-aliasing filters, errors in multiplexers and S/H circuits; definition and evaluation of ENOB. Power devices (1 CFU) - MOS and BJT devices, SOA - Driving ON/OFF loads

Practice classes address limited-complexity designs, related with subject of the previous lectures. The design includes numerical evaluation, which requires hand-held scientific calculators (personal). Experimental labs are focused towards verification of the circuits designed in the practice classes, with measurements on these same circuits. The course includes a total of 7 or 8 lab sessions. Labs are carried out by teams of 3/4 students, who must prepare a homework before the lab session, and deliver a report on the design lab measurements. The reports are verified, and taken into account for the final mark.

A textbook is in preparation and will be possibly ready for the course start. If not draft versions of the book chapters will be made available. A textbook which includes most of the addressed subject is: Design with Operational Amplifiers and Analog Integrated Circuits (III Edition), McGraw-Hill, 2002. Radio systems and PLLs are however described in: D. Del Corso, Elettronica per Telecomunicazioni, McGraw-Hill, 2000 (in Italian, available as print-on-demand in the publisher’s website). Copies of slides used in the lectures, examples of written tests, instruction manuals for the lab are available from the course website.

Modalità di esame: Prova scritta (in aula); Prova orale obbligatoria; Prova pratica di laboratorio;

Exam: Written test; Compulsory oral exam; Practical lab skills test;

... The final assessment includes a written test and an oral discussion. The written test consists of 2-3 numerical design exercises, related with the main subjects addressed in the course (analog circuits, A/D/A conversion systems and circuits, radio systems and PLLs,). Each exercise may have 4-6 questions; to pass the exam, one must deliver correct answer for at least the first two questions of each problem. The total time for the written test is 1,5 hours. The oral discussion lasts around 20-30’, and concerns all the subjects addressed in the lessons plus a short verification of the student capabilities in working in a electronic lab. The final mark is a weighted average of written test and oral discussion plus lab reports evaluation (0-2 points). The mark can be improved by developing mini-projects (agreed with the professor), or by preparing good notes from the lectures (to be used in the following years).

Gli studenti e le studentesse con disabilità o con Disturbi Specifici di Apprendimento (DSA), oltre alla segnalazione tramite procedura informatizzata, sono invitati a comunicare anche direttamente al/la docente titolare dell'insegnamento, con un preavviso non inferiore ad una settimana dall'avvio della sessione d'esame, gli strumenti compensativi concordati con l'Unità Special Needs, al fine di permettere al/la docente la declinazione più idonea in riferimento alla specifica tipologia di esame.

Modalità di esame: Prova orale obbligatoria; Prova scritta tramite PC con l'utilizzo della piattaforma di ateneo;

Written test (40 min-1h): From 6 to 8 questions covering the following arguments: BJT – MOS single transistor design (bias point selection, current or voltage spectrum in presence of filters, nonlinear BE junction, small signal gain and dynamics) PLL system design and implementation (filter parameters, phase detector, vco, impact on phase error, PLL as coherent demodulator) ADC-DAC systems (block diagram, dimensioning of the building blocks like S/H, antialiasing filter, DAC) RF transceiver (structure, heterodyne and homodyne implementation, main building blocks) Laboratory: Spice implementation of different building blocks, questions on the practical mounting on breadboard and measurements seen during the course (and in general to be known by any electrical engineer) The written test will be given by the EXAM platform adopting the respondus software and will be considered passed if 80% of the questions are answered positively. In this case it leads to the oral exam Oral exam (20-40 min) From 2 to 3 questions covering all the program, with the possibility to draw block schemes, circuits Final grade: 100% of the oral exam. The written test is a prerequisite to attend the oral one

Modalità di esame: Prova scritta (in aula); Prova orale obbligatoria; Prova scritta tramite PC con l'utilizzo della piattaforma di ateneo;

Written test (40 min-1h): From 6 to 8 questions covering the following arguments: BJT – MOS single transistor design (bias point selection, current or voltage spectrum in presence of filters, nonlinear BE junction, small signal gain and dynamics) PLL system design and implementation (filter parameters, phase detector, vco, impact on phase error, PLL as coherent demodulator) ADC-DAC systems (block diagram, dimensioning of the building blocks like S/H, antialiasing filter, DAC) RF transceiver (structure, heterodyne, and homodyne implementation, main building blocks) Laboratory: Spice implementation of different building blocks, questions on the practical mounting on breadboard and measurements seen during the course (and in general to be known by any electrical engineer) The written test will be given by the EXAM platform adopting the respondus software and will be considered passed if 80% of the questions are answered positively. In this case, it leads to the oral exam Oral exam (20-40 min) From 2 to 3 questions covering all the program, with the possibility to draw block schemes, circuits Final grade: 100% of the oral exam. The written test is a prerequisite to attend the oral one