Caricamento in corso...
Testing and fault tolerance
01RKZOV, 01RKZOQ, 01RKZQW
A.A. 2022/23
Course Language
Inglese
Degree programme(s)
Master of science-level of the Bologna process in Ingegneria Informatica (Computer Engineering) - Torino
Master of science-level of the Bologna process in Ingegneria Elettronica (Electronic Engineering) - Torino
Master of science-level of the Bologna process in Mechatronic Engineering (Ingegneria Meccatronica) - Torino
Course structure
| Teaching | Hours |
|---|---|
| Lezioni | 40 |
| Esercitazioni in aula | 10 |
| Esercitazioni in laboratorio | 10 |
| Tutoraggio | 27,5 |
Lecturers
| Teacher | Status | SSD | h.Les | h.Ex | h.Lab | h.Tut | Years teaching |
|---|---|---|---|---|---|---|---|
| Sonza Reorda Matteo | Professore Ordinario | IINF-05/A | 30 | 0 | 0 | 0 | 9 |
Co-lectures
Context
| SSD | CFU | Activities | Area context | ING-INF/05 | 6 | B - Caratterizzanti | Ingegneria informatica |
|---|
2022/23
The usage of electronic systems in applications where failures may results in critical consequences (e.g., in space, aircrafts, automobiles, trains, biomedical equipment) requires ensuring that the probability of a failure does not overcome some maximum threshold. This can be achieved by identifying and removing defective products (test) and by making products resilient to faults (fault tolerance). The course introduces methods and techniques for the design of reliable electronic circuits and systems, with special emphasis on the test performed to identify products affected by hardware faults, and on the solutions to harden electronic products with respect to faults and to the techniques to estimate the probability that possible faults may force them to produce failures.
The usage of electronic systems in applications where failures may results in critical consequences (e.g., in space, aircrafts, automobiles, trains, biomedical equipment) requires ensuring that the probability of a failure does not overcome some maximum threshold. This can be achieved by identifying and removing defective products (test) and by making products resilient to faults (fault tolerance). The course introduces methods and techniques for the design of reliable electronic circuits and systems, with special emphasis on the test performed to identify products affected by hardware faults, and on the solutions to harden electronic products with respect to faults and to the techniques to estimate the probability that possible faults may force them to produce failures.
- Knowledge of the concepts of testing and dependability.
- Knowledge of the main techniques used for testing a digital circuit.
- Knowledge of the main techniques used for testing an embedded system.
- Knowledge of the basic techniques used for hardening an electronic products with respect to possible faults.
- Knowledge of the main techniques for estimating the reliability of an electronic system.
- Capability of developing the test plan for a digital device or embedded system
- Capability to use the main software tools for testing an embedded system: fault simulators, automatic test pattern generators, automatic scan chain inserters.
- Knowledge of the concept of Built-In Self-Test (BIST) and Boundary Scan (BS).
- Knowledge of the concept of Failure Mode and Effect Analysis (FMEA).
- Capability of designing BIST hardware modules.
- Knowledge of the concepts of testing and dependability.
- Knowledge of the main techniques used for testing an electronic circuit.
- Knowledge of the main techniques used for testing an embedded system.
- Knowledge of the basic techniques used for hardening an electronic products with respect to possible faults.
- Knowledge of the main techniques for estimating the reliability of an electronic system.
- Capability of developing the test plan for a digital device or embedded system
- Capability to use the main software tools for testing an embedded system, such as fault simulators, automatic test pattern generators, automatic scan chain inserters.
- Knowledge of the concept of Built-In Self-Test (BIST) and Boundary Scan (BS).
- Knowledge of the concept of Failure Mode and Effect Analysis (FMEA).
- Capability of designing simple BIST hardware modules.
The course is better followed if the student owns the knowledge about
• Digital system design
• Microelectronics.
The course is better followed if the student owns the knowledge about
• Digital system design
• Microelectronics
• Computer architectures.
1. Introduction to test and dependability (1 credit)
a. Dependability: definition, attributes
b. Fault models (temporary and transient): stuck-at, bridge, open, delay, SEU, SET
c. Test of ICs, boards and systems
d. Defect level: definition and evaluation
e. ATEs
2. Techniques and tools for generating test stimuli for combinational and sequential modules (1 credit)
a. Fault simulation
b. Automatic Test Pattern Generation
3. Techniques and tools for testing specific modules (1 credit)
a. Memory test
b. Processor test
4. Design for Testability techniques (1 credit)
a. Scan
b. BIST
c. Boundary Scan
d. System on Chip test (IEEE 1500 and 1687)
5. Board test (0.5 credit)
a. Main steps in PCB test
b. IEEE 1149.1
6. Basics in fault tolerant system design (1.5 credits)
a. Basic fault tolerant design solutions (hw redundancy, information redundancy, time redundancy)
b. Reliability evaluation (FMEA, radiation experiments, fault injection)
1. Introduction to test and dependability (1 credit)
a. Dependability: definition, attributes
b. Fault models (temporary and transient): stuck-at, bridge, open, delay, SEU, SET
c. Test of ICs, boards and systems
d. Defect level: definition and evaluation
e. ATEs
2. Techniques and tools for generating test stimuli for combinational and sequential modules (1 credit)
a. Fault simulation
b. Automatic Test Pattern Generation
3. Techniques and tools for testing specific modules (1 credit)
a. Memory test
b. Processor test
4. Design for Testability techniques (1 credit)
a. Scan
b. BIST
c. Boundary Scan
d. System on Chip test (IEEE 1500 and 1687)
5. Board test (0.5 credit)
a. Main steps in PCB test
b. IEEE 1149.1
6. Basics in fault tolerant system design (1.5 credits)
a. Basic fault tolerant design solutions (hw redundancy, information redundancy, time redundancy)
b. Reliability evaluation and risk assessment (FMEA, radiation experiments, fault injection)
Laboratory activities are an integral part of this course. During the lab sessions students will face the practical aspects introduced by lectures. Lab sessions will allow students to work with commercial tools for Fault Simulation, Scan Insertion, Automatic Test Pattern Generation and Boundary Scan test development. Students will also be asked to develop assignments concerning the course subjects. A typical assignment consists in implementing a given test solution (whose main characteristics have been described in the lectures) for a specific case study.
The course will be composed of
- lectures
- lab sessions
- activities autonomously performed by students (assignments).
Laboratory activities are an integral part of this course. During the lab sessions students will face the practical aspects introduced by lectures. Lab sessions will allow students to work with commercial tools for Fault Simulation, Scan Insertion, Automatic Test Pattern Generation and Boundary Scan test development. Students will also be asked to develop assignments concerning the course subjects. Only students who regularly followed the lab sessions can work on assignments. A typical assignment consists in implementing a given test solution (whose main characteristics have been described in the lectures) for a specific case study.
Students may benefit of the following textbook:
M. Bushnell, V. Agrawal:
Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits
Kluwer Academic Publisher, 2000
Slides will be provided to students registered to the course through the Student Teaching Portal, as well as any additional non-copyrighted information material that will be used in the course.
Students may benefit of the following textbook:
M. Bushnell, V. Agrawal:
Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits
Kluwer Academic Publisher, 2000
Slides will be provided to students registered to the course through the Student Teaching Portal, as well as any additional non-copyrighted information material that will be used in the course.
Modalità di esame: Prova scritta (in aula); Prova orale obbligatoria; Elaborato progettuale in gruppo;
Exam: Written test; Compulsory oral exam; Group project;
...
The exam aims at verifying the student's knowledge about the course topics and his/her ability to apply the presented techniques to some specific case.
The exam will be based on a written part in which the students will be asked to answer to some (about 5) open questions and to solve exercises. Each question/exercise contributes with up to 6 points to the final score. The exam will last for about 90 minutes. Students will not be allowed to access any material during the exam.
If the student achieves at least 18 points in the written exam, he/she may ask for an oral exam. During the oral exam the student will be asked to report about issues and solutions described during the course, or solve specific problems related to the course topics. The oral exam is organized in about 3 questions and can increase or decrease the score achieved with the written exam by up to 6 points.
The students will be allowed to work on an assignment (typically, in groups of 1 or 2 people) which could increase the score of the written exam by up to 5 points.
Gli studenti e le studentesse con disabilità o con Disturbi Specifici di Apprendimento (DSA), oltre alla segnalazione tramite procedura informatizzata, sono invitati a comunicare anche direttamente al/la docente titolare dell'insegnamento, con un preavviso non inferiore ad una settimana dall'avvio della sessione d'esame, gli strumenti compensativi concordati con l'Unità Special Needs, al fine di permettere al/la docente la declinazione più idonea in riferimento alla specifica tipologia di esame.
Exam: Written test; Compulsory oral exam; Group project;
The exam aims at verifying the student's knowledge about the course topics and his/her ability to apply the presented techniques to some specific cases.
The exam will be based on a written part in which the students will be asked to answer to some (about 5) open questions and exercises. Each question/exercise contributes with up to 5 points to the final score. The exam will last for about 90 minutes. Students will not be allowed to access any material during the exam.
If the student achieves at least 15 points in the written exam, he/she can ask for an oral exam. During the oral exam the student will be asked to report about issues and solutions described during the course, or solve specific problems related to the course topics. At the end of the oral exam the student receives a score between 0 and 25 taking into account his/her performance in both the written and oral exams.
If the student achieves at least 18 points in the written exam, he/she can directly ask for recording the score.
Any student who successfully worked (in groups of 1 to 3 people) to the assignments can get up to 6 extra points which will be added to the exam score (if this is greater or equal than 18).
In addition to the message sent by the online system, students with disabilities or Specific Learning Disorders (SLD) are invited to directly inform the professor in charge of the course about the special arrangements for the exam that have been agreed with the Special Needs Unit. The professor has to be informed at least one week before the beginning of the examination session in order to provide students with the most suitable arrangements for each specific type of exam.