At the end of the class, the student shall acquire: - knowledge of the basic cells used in complex analog ICs; - ability to design basic gain stages in order to fulfill a set of specifications; - knowledge of technology parameters (fabrication tolerances and device matching) and their effect of circuit performance; - ability to analyze and design continuous-time gain stages like Miller OTAs and Folded Cascode OTAs; - ability to analyze and design integrated current sources and bias circuits; - ability to analyze and design bandgap voltage references; - ability to analyze and design switched-capacitors gain stages and filters.

Circuit theory, Analog circuits, Solid State Devices (Diodes, BJTs, MOST)

- Basic analog cells; - Review on CMOS technology, active and passive device models - fabrication tolerances and device mismatch - Nwell, metal, active, poly and select layers (2 cfu) - Bias circuits. Voltage and current reference - Folded-cascode and Miller operational trasconductance amplifiers (OTAs) - Output stages - Fully differential OTAs. Common mode feedback. (3 cfu) - Discrete-time signal processing fundamentals: sampling and z-transform - Design of digital filters - Switched-capacitor circuits and filters (1 cfu)

Exercise lectures address limited-complexity designs that are related with the topics presented in the previous lectures. In the CAD labs the students have to design circuits similar to those presented in the exercise lectures and the performance of such circuits must be verified through CAD based analysis (Cadence Virtuoso design environment). In addition to use Cadence in the labs, the students will have the possibility to connect remotely to the CAD server and repeat (or complete) the lab design at home. The server will be accessible both during the semester and after its conclusion.

Slides used during lectures will be available to the students. Textbooks to be used as additional reference: 1. B. Razavi, Design of Analog CMOS Integrated Circuits, Mc GrawHill, 2006 (2nd edition) 2. P. R. Gray, P. J. Hurst, S. H. Lewis, R. G. Meyer, Analysis and Design of Analog Integrated Circuits, Wiley, 2009 (5th edition) 3. T. Carusone, D. Johns, K. Martin, Analog Integrated Circuit Design, Wiley, 2012 (2nd edition) 4. R. J. Baker, CMOS Circuit Design, Layout, and Simulation, Wiley-IEEE Press, 2010 (3rd edition) 5. P. E. Allen, D. R. Holberg, CMOS Analog Circuit Design, Oxford, 2012 (3rd edition) 6. R. J. Baker, CMOS: Mixed-Signal Circuit Design, Wiley-IEEE Press, 2008 (2nd edition)

Lecture slides; Lecture notes; Video lectures (current year);

You can take this exam before attending the course

Exam: Compulsory oral exam; Individual project; Group project;

Oral examination on analysis and design of analog integrated circuits (about 30min). As far the evaluation of the lab activity is concerned, there are two possible paths (student choice): 1) The first one requires that the student submit a report on one of the last two design labs: in this case the final grade is a weighted average of the oral exam (weight 0.8) and lab report (weight 0.2). 2) The second possibility is to present a report on a CAD design of a more complex circuits (prepared alone or within a group of two students – depend in on the project complexity) selected in agreement with the Professor. in this case the final grade is a weighted average of the oral exam (weight 0.2) and the report on the design presented during the oral discussion (weight 0.8). The report in both cases can be submitted just before the exam and will be discussed during it. In the case of the group project a powerpoint presentation is possible. Both the oral exam and the lab report aim to determine the level of capability of the student to design and implement a simple analog circuits, like an op-amp or a bandgap reference. In case the student chooses to do an independent project on the design of a more complex circuit, the discussion will focus on the design of the individual blocks and questions will be asked to ascertain that student design choices have been adequate and fully understood. When necessary, during the exam, students will be asked to use cadence virtuoso tools while describing their lab report or their design.

In addition to the message sent by the online system, students with disabilities or Specific Learning Disorders (SLD) are invited to directly inform the professor in charge of the course about the special arrangements for the exam that have been agreed with the Special Needs Unit. The professor has to be informed at least one week before the beginning of the examination session in order to provide students with the most suitable arrangements for each specific type of exam.