Many algorithms in signal processing, data analytics, machine learning, digital communication, and cryptography systems involve complicated computations. They can be translated to different hardware implementations whose silicon area, throughput, and power consumption have large variations. This course introduces highly-practical methodologies and techniques that can be broadly used to improve the efficiency and achieve speed-area-power tradeoffs in the design of hardware implementation architectures for various algorithms. Different from circuit-level optimizations, these techniques focus on algorithmic and architectural transformations, which can lead to much more significant improvements on silicon area, speed, and power consumption. With the understanding of the tradeoffs, appropriate architectures can be developed to meet the requirements of target applications. Efficient implementation architectures of commonly used arithmetic functions will also be discussed. The goal of this course is to equip students with techniques and knowledge for translating advanced algorithms to efficient hardware implementations so that they can hold advantages positions in CHIPS Act-related research and career.

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GUEST LECTURE Xinmiao Zhang - Ohio State University CV: Xinmiao Zhang, currently a Professor at The Ohio State University and a member of the Translational Data Analytics Institute, earned her Ph.D. in Electrical Engineering from the University of Minnesota. She has both academic and industry experience, having worked as a Senior Technologist at Western Digital/SanDisk (2013-2017). Her research focuses on VLSI architectures, error-correcting codes, cryptography, and hardware security, with significant contributions in ultra-high-speed decoding and post-quantum cryptography. She has received several awards, including the NSF CAREER Award (2009), and has held key roles in IEEE, such as Vice President-Technical Activities of the Circuits and Systems Society (2022-2023). The topics that will be discussed in this course are listed below. • Fast Convolution • Algorithmic strength reduction in transformations

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Presentazione orale

P.D.1-1 - Novembre