PORTALE DELLA DIDATTICA

PORTALE DELLA DIDATTICA

PORTALE DELLA DIDATTICA

Elenco notifiche



Computer architectures

02LSEOV, 02LSEOQ

A.A. 2024/25

Course Language

Inglese

Degree programme(s)

Master of science-level of the Bologna process in Ingegneria Informatica (Computer Engineering) - Torino
Master of science-level of the Bologna process in Ingegneria Elettronica (Electronic Engineering) - Torino

Course structure
Teaching Hours
Lezioni 71
Esercitazioni in aula 9
Esercitazioni in laboratorio 19,5
Lecturers
Teacher Status SSD h.Les h.Ex h.Lab h.Tut Years teaching
Ferrero Renato   Professore Associato IINF-05/A 23 9 1,5 0 2
Co-lectures
Espandi

Context
SSD CFU Activities Area context
ING-INF/05 10 B - Caratterizzanti Ingegneria informatica
2024/25
The course, a mandatory component of the Master’s Degree in Computer Engineering, is taught in English during the first semester of the first year. It plays a crucial role in equipping students with knowledge on the architecture of elaboration systems, with a specific focus on microprocessor-based systems. The course delves into the various components of an elaboration system, from the microprocessor's internal architecture to the management of peripheral devices. It also includes a comprehensive study of programming at the assembly level.
At the end of the course, the students will gain: • Knowledge of several processor architectures, with particular attention paid to pipelined processors and the ARM family • Knowledge of superscalar, multi-process, and multithread architectures • Knowledge of the memory hierarchy (for example, cache L1 and L2) • Knowledge of system bus, CPU, and I/O characteristics. Throughout the course, students will have the opportunity to apply the acquired knowledge to program the functionalities of the processor, manage the I/O, and design the interface. They will be empowered to write firmware in assembly code and use ARM-based boards, focusing on their programming and debugging. This hands-on experience will enhance their practical skills and make them more capable in the field of computer engineering.
• Knowledge of the architecture of elaboration systems: processor structure, memory organization, and peripheral management • Knowledge of basic functionalities of operating systems • Capability to develop programs in C and assembler language.
• Advanced description of the microprocessor architecture • Introduction to modern microprocessor architectures • CISC, RISC, and superscalar processor architectures: analysis of their behavior and performance • Pipeline, hazards, stalls and counter-measurements • Development flow of embedded system applications using a development board based on an ARM processor • Advanced programming techniques for embedded systems (C and ARM): theory and practice • Advanced programming techniques for an ARM-based board system: LEDs, buttons, timers, GP IO, loudspeaker, potentiometer, UART port.
Detailed program: Intro to computer design Instruction set principles Example of a RISC processor Instruction Set Architecture Pipelining intro, hazards, forwarding, and stalls. Integer operations Multi-cycle pipelined processors ILP and static optimization techniques Branch Prediction Unit Dynamic scheduling HW-based speculation Multiple issue and i7, a8, VLIW processors Task Level Parallelism Cache memories Virtual memory Intro ARM processors ARM processor instruction set ARM software interrupts ARM-based System-on-Chip - HW interrupt - interrupt controller ARM-based System-on-Chip - HW interrupt II - GPIO Cross-compile C + ASM - use of libraries Cross-compile ASM + C - ABI standard ARM-based System-on-Chip - clock/power management ARM-based System-on-Chip - HW interrupt III - timers UART Standard and Button Bouncing Display and speakers libraries ARM-based System-on-Chip - HW interrupt - advance interrupt controller.
• Class lectures: 50% of the course duration • Extensive class exercise time: 30% of the course duration • Assisted laboratories: 20% of the course duration. Students are highly invited to interact with Lecturers, at lecture, exercise, and laboratory slots.
J.L. Hennessy and D.A. Patterson, Computer Architecture: a Quantitative Approach, Morgan Kaufmann Publishers, Inc., VI Edition, 2017 W. Hohl and C. Hinds, ARM Assembly Language: Fundamentals and Techniques, Crc Press, 2nd edition, 2016 J. Yiu, The definitive guide to the ARM Cortex M3, Newnes, 2009. Steve Furber, ARM system-on-chip architecture, Addison-Wesley, 2000.
Lecture slides; Lab exercises;
Exam: Computer lab-based test; Optional oral exam;
The exam consists of a written part and an optional part, at the discretion of the teacher. The written part is divided into two sub-parts: 1. The first sub-part consists of open&closed questions about subjects covered during lectures, such as time evaluation and hardware cost in modern architectures. While this sub-part is being run, it is not possible to use any book or other material. 2. The second sub-part consists of the development of a program in ARM assembly and C language. running on the board. While this sub-part is being run, it is possible to use only printed books and/or documents in electronic format downloaded from the web site of the course (Portale della Didattica). The written part (=first+second sub-parts) lasts 2 and has to be passed in both its two sub-parts. Failing one of the two sub-parts will imply a rejection. In the next few days, the student is required to provide a full working code for the correction of the second part. A project carried out during the final laboratories will be evaluated and can lead to up to 4 extra points to be added to the test grade if positive. Regardless of the student's choice, the teacher has the right to proceed with the oral exam if he/she deems further study appropriate. If the total score achieved is greater than or equal to 31.5 (before rounding), it will result in the awarding of honors. Overall, the exam is targeted at evaluating the students both from their abilities to design, write and run assembly programs, and their knowledge of modern computing systems architectures.
In addition to the message sent by the online system, students with disabilities or Specific Learning Disorders (SLD) are invited to directly inform the professor in charge of the course about the special arrangements for the exam that have been agreed with the Special Needs Unit. The professor has to be informed at least one week before the beginning of the examination session in order to provide students with the most suitable arrangements for each specific type of exam.
Esporta Word