- Knowledge of Electronic Design Automation flows with particular emphasis on synthesis and optimization techniques at different levels of abstraction, from high- to logic-level; - Modeling of digital circuits and abstract data structures used in EDA tools; - Knowledge of behavioral- and logic-level synthesis methodologies; - Understanding of the main optimization techniques and their algorithms for different cost functions (Area, Delay, Power consumption) - Practical skills in commercial synthesis tools, industrial deep-submicron CMOS technologies, TCL scripting language, C/C++ for high-level synthesi

- Software programming (data structures and algorithms) - Basics of digital electronics (CMOS and logic circuits, computer architecture) - Hardware description languages (Verilog/VHDL)

- Introduction to electronic design automation for digital circuits and basic concepts behind synthesis and optimization (1 credit) - Computer-aided design methods, techniques, and algorithms at different levels of abstraction (3 credits): * Synthesis and optimization algorithms at the behavioral level (Scheduling, Sharing & Binding algorithms, and programming strategies to drive high-level synthesis) * Synthesis and optimization algorithms at the logic level (Boolean and Algebraic methods) * Technology mapping (Boolean and Structural matching) - Computer-aided design for low-power circuits (2 credits): * Power modeling * Low-power design techniques at behavioral and logic level

- The course includes both exercises during regular classes and lab practices. - Theory: All the theoretical aspects will be introduced during the regular classes [ ~33h] - Exercises: will show numerical examples of the main techniques and algorithms introduced during the classes [~9h]. - Lab practice (groups of 2-3 students): aim at providing students with technical skills on industrial EDA tools and commercial CMOS libraries for the design of digital circuits, like synthesis tools at logical and behavioral level, simulators, tools for power analysis, area and delay estimation; the scripting language TCL will be introduced as the main interface to those tools.

Class handouts and additional material will be made available on the course webpage. User guides for lab sessions will be made available as well. Main reference book: G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994.

Lecture slides; Lecture notes; Text book; Exercises; Lab exercises;

Exam: Written test; Group project;

Learning outcomes - Understanding of the digital design flow, the abstraction hierarchy, and the main procedures/methodologies adopted today in commercial flows - Ability to recognize and use the most appropriate optimization algorithm for latency, area, and power minimization - Understanding of the different modeling strategies adopted in a typical digital design flow - Ability to build and test optimization algorithms deployed as a plug-in into commercial synthesis tools Rules and procedures for the exam. The exam consists of two parts. - The first one (90% of the final score) is a written test including both numerical exercises and open-answer questions. The time allowed for the test is 2 hours, closed books; the maximum score for this part is 27 points. - The second part (10% of the final score) consists of a group project in which some of the techniques described in the course will be implemented on the EDA framework used during the lab sessions; the maximum score for this project is 3 points. The final score is the sum of the score obtained in the two parts.

In addition to the message sent by the online system, students with disabilities or Specific Learning Disorders (SLD) are invited to directly inform the professor in charge of the course about the special arrangements for the exam that have been agreed with the Special Needs Unit. The professor has to be informed at least one week before the beginning of the examination session in order to provide students with the most suitable arrangements for each specific type of exam.