Applying the studied methods for the analysis of combinational and sequential circuits. Applying the studied methodologies for the design of basic combinatorial and sequential circuits. Modeling digital circuits by means of Hardware Description Languages such as VHDL. Designing complete digital systems starting from the assigned specifications. Programming a modern configurable logic device (FPGA). Understanding the architecture and functionalities of different memory components Understanding the internal features and capabilities of modern microcontrollers. Developing microcontroller-based applications starting from assigned specifications.

Boole's Algebra; elementary gates; basics in electronic devices; basics in C programming language and computer architecture.

Combinational circuits: relevant circuits, timing, synthesis techniques for basic circuits, arithmetic circuits. (0.5 CFU) Sequential circuits: elementary circuits, flip flops, FSMs. (1 CFU) Complex architectures (ASM charts, datapath and control unit). (1 CFU) Hardware Description Languages (VHDL): statements, data structures, and coding techniques for hardware description and modeling (1.5 CFU) Microcontrollers: internal architecture, programming model, peripherals, development tools (2 CFU) Memories: circuits, architectures, and applications. (1 CFU) Programmable devices (PLD, FPGA). (1 CFU)

Practice classes will focus on a number of assigned digital designs: 1) VHDL as a language for design entry (behavioural simulation, synthesis, post place & route simulation) 2) Application design on an FPGA board (design entry, simulation, synthesis) 3) FPGA configuration and test 4) Microcontroller technology : development of simple projects (C language), test on STM32 microcontroller Laboratory sessions consist of the development, synthesis, and implementation of dedicated digital designs described using VHDL language or microcontroller-based applications. Evaluation boards will be available to test the designs. Overall, laboratory assignments will be completed by groups of 3 or 4 students. A report is required for each laboratory session and it will be considered in the final grade. Assignments must be completed and delivered within specific dates distributed during the spring term.

The learning material used for the lessons is made available through the course website. This includes notes provided by the professor, datasheets of electronic components, free ebooks and past written tests. Reference textbooks: "Fundamentals of Digital Logic with VHDL Design (Third Edition)" Stephen Brown and Zvonko Vranesic , Mc Graw Hill “Introduction to Microcontrollers”, Günther Gridling, Bettina Weiss, Vienna University of Technology, 2007 “Mastering STM32”, Carmine Noviello, Lean Publishing, 2017. Free ebooks: “Free Range VHDL”, Bryan Mealy, Fabrizio Tappero, 2016 “The VHDL Cookbook”, Peter J. Ashenden, 1990 “Introduction to Embedded Systems - Interfacing to the Freescale 9S12”, Jonathan W. Valvano, 2010

Lecture slides; Lecture notes; Text book; Exercises; Exercise with solutions ; Lab exercises; Video lectures (previous years); Simulation tools;

Exam: Written test; Compulsory oral exam; Group project;

The exam has three components: 1) Written test on the whole set of covered topics. Questions include at least one (simple) design problem to be solved and two/three open answer questions, where you have to describe what you know about a given subject. There are no multiple-choice questions. This component assigns up to 21 points in the 30-point scale. 2) Evaluation of the group projects, based on material delivered within the given deadlines. Late deliveries will not be evaluated. This component assigns up to 9 points. 3) Oral exam, mandatory, covering questions about the completed projects, questions about the written test (if necessary), additional questions on any course topic. In the written test, the available time is 2 hours. The questions cover all course topics and they intend to verify the acquired knowledge and capabilities. The design problem requires understanding the initial specifications, developing a detailed datapath architecture, to properly model the control unit, and describing one or multiple elements by means of VHDL. No books and notes are admitted. Each question has a uniform distribution of weights. However, these weights may be slightly modified (by no more than 20%) after the correction of tests, based on the statistical distribution of marks. The evaluation of the written test initially assigns a mark in the 0 to 30 range (passing threshold = 18). Passing marks are then multiplied by 21/30 (range 12.6 to 21) . The evaluation of the laboratory projects gives additional points up to a maximum of 9/30, depending on: quality of the delivered code (functional correctness, synthesizability, readability, …), and quality of the report (clarity, completeness, …). The oral exam is accessible only if the written test has been passed (mark >= 18/30 or >=12.6/21). One of the main roles of the oral exam is evaluating the individual contribution of a student in the delivered group projects. The oral exam can correct the mark resulting from the sum of the two previous evaluations by +/- 3 points.

In addition to the message sent by the online system, students with disabilities or Specific Learning Disorders (SLD) are invited to directly inform the professor in charge of the course about the special arrangements for the exam that have been agreed with the Special Needs Unit. The professor has to be informed at least one week before the beginning of the examination session in order to provide students with the most suitable arrangements for each specific type of exam.