PORTALE DELLA DIDATTICA

PORTALE DELLA DIDATTICA

PORTALE DELLA DIDATTICA

Elenco notifiche



GPU Programming and CUDA Kernel Optimization

01XBHRV

A.A. 2026/27

Course Language

Inglese

Degree programme(s)

Doctorate Research in Ingegneria Elettrica, Elettronica E Delle Comunicazioni - Torino

Course structure
Teaching Hours
Lezioni 20
Lecturers
Teacher Status SSD h.Les h.Ex h.Lab h.Tut h.Sem Years teaching
Prono Luciano   Ricercatore L240/10 IINF-01/A 20 0 0 0 0 1
Co-lectures
Espandi

Context
SSD CFU Activities Area context
*** N/A *** 4    
This course introduces GPU programming through CUDA with a focus on understanding performance at the kernel level. Students explore how modern GPUs execute parallel workloads and how memory hierarchy and execution structure affect efficiency. The course centers around the design and iterative improvement of matrix multiplication kernels as a concrete case study for learning core GPU concepts. Emphasis is placed on reasoning about design choices, understanding performance tradeoffs, and interpreting how low-level implementation details map to hardware behavior.
This course introduces GPU programming through CUDA with a focus on understanding performance at the kernel level. Students explore how modern GPUs execute parallel workloads and how memory hierarchy and execution structure affect efficiency. The course centers around the design and iterative improvement of matrix multiplication kernels as a concrete case study for learning core GPU concepts. Emphasis is placed on reasoning about design choices, understanding performance tradeoffs, and interpreting how low-level implementation details map to hardware behavior.
- Basic linear algebra (matrix operations) - Programming experience (C++ and Python) - Familiarity with basic computer architecture concepts (CPU execution, memory hierarchy, instruction-level parallelism)
- Basic linear algebra (matrix operations) - Programming experience (C++ and Python) - Familiarity with basic computer architecture concepts (CPU execution, memory hierarchy, instruction-level parallelism)
- GPU architecture fundamentals (SIMT, warps, occupancy) - Memory hierarchy (global, shared, registers, caches) - CUDA programming model (threads, blocks, grids) - Kernel optimization strategies (tiling, unrolling, memory reuse) - Performance concepts (bandwidth, latency, coalescing)
- GPU architecture fundamentals (SIMT, warps, occupancy) - Memory hierarchy (global, shared, registers, caches) - CUDA programming model (threads, blocks, grids) - Kernel optimization strategies (tiling, unrolling, memory reuse) - Performance concepts (bandwidth, latency, coalescing)
In presenza
On site
Presentazione report scritto
Written report presentation
P.D.1-1 - Gennaio
P.D.1-1 - January