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Politecnico di Torino
Academic Year 2009/10
01GQCCI, 01GQCBP, 01GQCKY, 01GQCKZ
Integrated systems architecture
Master of science-level of the Bologna process in Electronic Engineering - Torino
Master of science-level of the Bologna process in Telecommunication Engineering - Torino
Master of science-level of the Bologna process in Electronic Engineering - Torino
Espandi...
Teacher Status SSD Les Ex Lab Tut Years teaching
Masera Guido ORARIO RICEVIMENTO O2 ING-INF/01 30 30 0 0 16
SSD CFU Activities Area context
ING-INF/01 5 C - Affini o integrative Discipline ingegneristiche
Esclusioni:
01KRT
Syllabus
Scheduling and resource allocation algorithms in SoC architectures.
- Partitioning techniques and on-chip communication strategies.
- Architecture of arithmetic building blocks: adders, multi-operand
adders, multipliers and dividers.
- Memory blocks architecture: single and multi-port memories, register
file, FIFO, LIFO.
- Control structures: hard-wired and microprogrammable FSM.
- ISA definition of IP: CISC, RISC, VLIW.

Programma definitivo per l'A.A.2009/10
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