Politecnico di Torino
Politecnico di Torino
Politecnico di Torino
Academic Year 2009/10
Master of science-level of the Bologna process in Computer Engineering - Torino
Teacher Status SSD Les Ex Lab Tut Years teaching
Lavagno Luciano ORARIO RICEVIMENTO PO ING-INF/01 4 0 1 0 3
SSD CFU Activities Area context
ING-INF/01 5 C - Affini o integrative Discipline ingegneristiche
01KRR; 01JEV
This course provides the students with an in-depth look of the circuit and layout design for CMOS standard cells, as well as an overview of modern Electronic Design Automation tools and flows. It starts by reviewing the behavior of MOS transistors and interconnect structures. Then it illustrates how transistors are combined to create logic gates for the main logic families, considering the corresponding area, delay, power and robustness trade-offs. Combinational and sequential gates, using both static and dynamic logic are discussed. Clocking strategies for sequential logic are described, as well as performance optimization strategies by transistor sizing. Finally it provides an overview of the complete RTL-to-GDSII flow that is used today for implementation of digital circuits.

Programma definitivo per l'A.A.2009/10

© Politecnico di Torino
Corso Duca degli Abruzzi, 24 - 10129 Torino, ITALY
WCAG 2.0 (Level AA)