This course provides the students with an in-depth look of the circuit and layout design for CMOS standard cells, as well as an overview of modern Electronic Design Automation tools and flows. It starts by reviewing the behavior of MOS transistors and interconnect structures. Then it illustrates how transistors are combined to create logic gates for the main logic families, considering the corresponding area, delay, power and robustness trade-offs. Combinational and sequential gates, using both static and dynamic logic are discussed. Clocking strategies for sequential logic are described, as well as performance optimization strategies by transistor sizing. Finally it provides an overview of the complete RTL-to-GDSII flow that is used today for implementation of digital circuits.