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Politecnico di Torino
Anno Accademico 2009/10
01JCLGH
Digital circuits design
Corso di L. Specialistica in Nanotecnologie Per Le Ict (To/Grenoble/Losanna) - Torino/Grenoble/Losanna
Docente Qualifica Settore Lez Es Lab Tut Anni incarico
SSD CFU Attivita' formative Ambiti disciplinari
ING-INF/01 2 B - Caratterizzanti Ingegneria elettronica
Obiettivi dell'insegnamento
To be able to create VHDL models of digital components for simulation and synthesis.
To be able to create testbench models and to learn verification techniques.
To learn modeling guidelines.
To develop a reference library of VHDLmodels.
To get a working knowledge of VHDL simulation and synthesis tools.
To position VHDL with respect to other languages (Verilog, SystemC).
Programma
Models in electronic design automation. Hardware description languages. Logic simulation. Architectural and logic synthesis. VHDL characteristics (language, design flow, modelling guidelines).

VHDL synthesis subset (IEEE Std 1076.3 and 1076.6). Examples of VHDL instructions synthesis.

Basic combinational and sequential elements. Controllers (finite state machines). Arithmetic units (adders, multipliers, ALU). Memories (registers, RAM, ROM, FIFO, LIFO). Digital filters. Interface circuits (UART, PCI). Processors. Testbenches and verification techniques.

Verilog and SystemC characteristics with examples. Comparison with VHDL. Common modelling techniques.
Statistiche superamento esami

Programma definitivo per l'A.A.2009/10
Indietro



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