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Politecnico di Torino
Academic Year 2015/16
01NOYOQ, 01NOYOV
Microelectronic systems
Master of science-level of the Bologna process in Electronic Engineering - Torino
Master of science-level of the Bologna process in Computer Engineering - Torino
Teacher Status SSD Les Ex Lab Years teaching
Graziano Mariagrazia ORARIO RICEVIMENTO RC ING-INF/01 27 12 21 9
SSD CFU Activities Area context
ING-INF/01 6 C - Affini o integrative Attivitā formative affini o integrative
Subject fundamentals
The course is taught in English.

The course is optional for the MSc-level programme in both Electronic Engineering and Computer Engineering. It will be offered in the second period of the first academic year. It aims at analyzing the design methodologies of complex microelectronic systems based on scalded MOS devices, considering the constraints and critical issues in designing architectural and microarchitectural blocks and detailing the technological aspects native to the design of structures based on devices and interconnections that are the state of the art od digital electronics. The analyzed aspects will be applied to some cases of study in laboratory sessions based on the use of specific CAD tools like HDL simulators, synthesizers, place&routers, layout editors, physical level simulators.
Expected learning outcomes
- Knowledge of MOS based topologies and of its technology, of the related digital gates of their description at different level of abstraction and of their performance (standard cell libraries)
- Knowledge of problems related to signal and power supply interconnects in integrated circuits and of the related design aspects
- Ability to design microarchitectural structures to be used as foundamental block in a digital integrated system for signal processing, as arithmetical blocks, hardwired and microprogrammed control systems and memory systems
- Knowledge of the manyfold techniques for describing, simulating and designing at circuit, architecture and system level, aiming at performance optimization (area, frequency, throughput, power consumption)
- Ability in using CAD tools aiding the design of integrated circuits on scaled technologies: HDL simulators, synthesizer, place&router, layout editors, physical level simulators
- Ability in analyzing specifications and contraints when designing complex digital systems and choosing the correct algorithm
- Ability in evaluating computational complexity, interconnect bandwidth and numerical choices (number precision and data representation) for complex elaboration circuits
- Knowledges on derivation of constraints on architecture, on resources allocation and scheduling
- Skill in the design of multi clock regimes
- Knowledge on control systems as hardwired and microprogrammed control units
- Basic knowledges on parallel integrated architectures
Prerequisites / Assumed knowledge
Basics of Digital Electronics (level of the first mandatory course of Digital Electronics or electronics for embedded syste, in the master degree program). Physics of semiconductors and elemntary models of MOS transistor should be known, as well as hardware description language (VHDl/VERILOG), complex architectures of microprocessors/DSP/microcontrollers.
Contents
.Case study of complex architectures as examples of microelectronic system: multithreading structure (T2 Ultrasparc), CISC/RISC structure (Pentium 4), structure for embedded systems (ARM 11). (0,5 CFU)

.Case study of internal microarchitecture for each of the systems mentioned (P4 adder, multiplier and logic block T2, ARM divider, windowed register file for multithreading from T2). Control units based on FSM, Hardwired and microprogrammed. (1,2 CFU)

.Digital MOS gates both combinational ads sequential based on different topologies (CMOS, domino, DCVSL, transmission gate, C2MOS, TSPC) analyzed for what concerns figures of merit used during the design of a integrated digital circuit (function, area, timing, power): abstraction levels of a library of gates, for low level simulation, physical design, synthesis and high level simulations. (1,5 CFU)

. Description of interconnects and their parasitic parameters; modeling and design criteria; Temporization and clock domains, technological phases. (1 CFU)

' Top down design of microelectronic systems based on previously described blocks: basics on architectural and topological solutions for performance optimization, synthesis techniques, physical design and post-layout verification (mainly in laboratory). (1,8 CFU).
Delivery modes
Due to the application oriented nature of this course laboratory sessions are planned aimed at designing complex digital circuits using specific CAD tools. Exercises will concern the design of basic blocks and the analysis of their performance thanks to the use of circuit simulators. Laboratory sessions will also concern the design of more complex architectures using VHDL language, their simulation and synthesis based on elementary library cells (scaled technologies), and the design of their layout using proper place & route CAD, verification algorithms and analyzing the tolerance to operating and process conditions.
The number of lab session is 6 and are based on group of 2 students. Each laboratory requires a final report which will be evaluated for the final score. The work can be completed as homework within three weeks from the laboratory day. For each labwork the student receive an evaluation and a suggestion on the main critical points found during the evaluation.
Texts, readings, handouts and other learning resources
Lectures notes of all the lectures ara available as well as laboratory guide. Books suggested are:
1) M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolicī: Digital Integrated CircuitsSecond Edition, Prentice-Hall,
2) N.Weste D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, Addison-Wesley
3) J.hennessy, d.Patterson, Computer Architecture: a Quantitative Approach, Addison-Wesley
Some suggested readings are in the form of research papers related to the most up-to-date subject analyzed.
The learning material is available through the official course website.
Assessment and grading criteria
The final examination consists in three part: E1 oral exam, E2, laboratory exercises, E3: a final project.

E1: The oral exam is related to the whole program and is related to all the subjects analyzed during classes and laboratories.
E2: The laboratory execises are evaluated for completeness, correctness and accuracy and timeliness.
E3: The project will consist in the development of an architecture as a case of study, in its simulationa and top-down design and optimization of the typical criticalities related to a mediun-high complex architecture based on a scaled technology. The project must be completed within the starting date of the academic year following the one of the attended course.

The student can choose among three different combinations:

Choice 1: the exam can be completed with part E1 (weight 60%) and part E2 (weight 40%), but the final evaluation will be saturated to a maximum of 26/30.

Choice 2: the exam can be completed with part E1 (weight 45%), part E2 (weight 15%), where the project (E3) is developed as a basic version based on several elements already developed during the lab. The final evaluation will be saturated to a maximum of 26/30.

Choice 3: he exam can be completed with part E1 (weight 45%), part E2 (weight 15%), where the project (E3) is developed as a more evolved versione enriched of innovative and more complex and challenging elements. The final evaluation will be saturated to a maximum of 30/30 cum laude.

Programma definitivo per l'A.A.2015/16
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