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Politecnico di Torino
Academic Year 2017/18
01NVLOQ
Digital microelectronics
Master of science-level of the Bologna process in Electronic Engineering - Torino
Teacher Status SSD Les Ex Lab Tut Years teaching
Lavagno Luciano ORARIO RICEVIMENTO PO ING-INF/01 39 0 21 0 6
SSD CFU Activities Area context
ING-INF/01 6 D - A scelta dello studente A scelta dello studente
Esclusioni:
01NOY
Subject fundamentals
The course goal is to provide the basic knowledge for the design of microelectronic digital systems ranging from the elementary devices to the functional blocks of average complexity. It will analyze the main issues and problems related to the different phases of the design and development of a digital integrated circuit together the main CAD tools.
Expected learning outcomes
Knowledge of the behaviour of the MOS device considering also short channel and velocity saturation effects.
Ability to derive a simplified model of the MOS device for digital applications from simulation or measurement data
Knowledge of the static, dynamic and power characteristics parameters of the logical inverter. Ability to determine them from simplified models of the devices.
Knowledge of the tools for describing logical circuits at the schematic level and of the tools for electrical simulation.
Knowledge of the basic CMOS bulk and SOI fabrication processes and of the tool for a description of a circuit at the layout level. Masks and design rules. Ability to describe simple gates at the .layout level, to verify them and to cross check them towards their schematic description.
Knowledge of complementary CMOS, pseudo nMOS, transmission gate based and dynamic logic structures.
Ability to design, from the functional description, the schematic description of simple complementary gates and to evaluate their dynamic parameters.
Knowledge of the basic methodology for sizing the gates of a complex circuit for delay optimization. Ability to apply these techniques for the optimization of a single critical path
Knowledge of elementary memory cells and of complex memory structures. Ability to analyze and simulate the behaviour of a static RAM memory.
Basic knowledge of the design flow from Register Transfer Level to design masks, and of the main EDA tools it uses.
Prerequisites / Assumed knowledge
Knowledge of the elementary large signal models of MOS and BJT transistors, Ability to use them for analyzing circuits with a single active device.
Knowledge of the transient electrical behaviour of RC networks.
Knowledge of the elementary logic functions, of Boolean algebra and of basic design techniques for logic circuits (Karnaugh maps and Finite State Machines).
Contents
Digital transistor models 4h
Fabrication process and its interface with layout and logic design 4h
Inverter circuit 6h
Static logic and multi-stage sizing 10h
Delay optimization 6h
Transmission gate and dynamic logic 8h
Interconnect and packaging 6h
Static and dynamic latches and registers 4h
ROM and RAM structures 4h
EDA tools for synthesis, placement and routing 6h
Delivery modes
Classroom exercises exemplify concepts described during lessons and include simple numerical exercises to be solved and discussed with the instructor.
Labs (typically 6 or 7) require the use of workstations and EDA tools to perform simple examples of schematic design and layout of circuits using CMOS technology. They are organized in groups of 3-4 people each.
Texts, readings, handouts and other learning resources
Apart from the slides used in class, available on "Portale della Didattica", the reference text book is "Digital Integrated Circuits" (2 edition), di J. Rabaey. A. Chandrakasan, B. Nikolic, Prentice Hall Ed., 2003
Assessment and grading criteria
The final exam is composed of a written and an optional oral part.
The written test includes both numerical exercises and multiple choice questions, about the main topics of the course, and lasts 1.5-2 hours. Neither books nor notes can be used. The maximum score is 30.
The oral can be requested by the student after seeing the graded written test, lasts for 15-20 minutes, and covers the entire course.
The final grade is a weighted average of the written and oral exam results, and can be 30 e lode after a very successful oral exam.

Programma definitivo per l'A.A.2017/18
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