Politecnico di Torino
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Politecnico di Torino
Academic Year 2012/13 (first time established in A.Y.2010/11)
01NWNOQ, 01NWNOV
Modeling and optimization of embedded systems
Master of science-level of the Bologna process in Electronic Engineering - Torino
Master of science-level of the Bologna process in Computer Engineering - Torino
Teacher Status SSD Les Ex Lab Years teaching
Lavagno Luciano ORARIO RICEVIMENTO PS ING-INF/01 48 0 12 4
SSD CFU Activities Area context
ING-INF/01 6 B - Caratterizzanti Ingegneria elettronica
Precedenze:
01NWM
Subject fundamentals

The course is taught in English.


This course introduces the main mathematical models and methods used for the synthesis and verification of embedded hardware and software. It assumes a good knowledge of digital hardware design (with VHDL or Verilog) and of software implementation (with C, C++ or Java) for embedded systems, including a basic knowledge of real-time operating systems. It provides the ability to select and use the best tools and methods for hardware/software co-design, as well as simulation and performance analysis. It provides knowledge about the SystemC language, synchronous languages and dataflow networks.
Expected learning outcomes

Knowledge of the main formal models and specification languages based on extended finite state machines and dataflow networks.
Knowledge of the hardware and software synthesis methods for synchronous languages and dataflow networks.
Knowledge of embedded software performance analysis techniques.
Ability to analyze at a high level the computational and communication requirements of an embedded application.
Ability to select the best specification languages and implementation tools, and to select a hardware/software architecture for an embedded system.
Ability to create a simulation model of an embedded system using a modeling language (e.g. SystemC)
Prerequisites / Assumed knowledge

Digital hardware design using Verilog or VHDL
C, C++ or Java programming
Architecture of at least one CPU, memory architecture and micro-controller.
Micro-controller peripheral programming.
Elements of real-time schedulability theory.
Contents

Topics (about 1/2 credit each):
Characteristics of embedded systems, architectures and design flows.
Control-dominated systems and data-dominated systems.
SystemC language: syntax and semantics. Usage examples.
SystemC design at Transaction level (TLM) and Register Transfer Level (RTL).
Extended Finite State machines. Synchronous (Moore and Mealy) and asynchronous composition.
Synchronous languages: StateCharts, Esterel and ECL. Control constructs (emit, await, abort, parallel). Usage examples.
Hardware and software synthesis techniques for Esterel. Interfacing methods with operating systems and peripherals.
Formal property verification (liveness and safety) using synchronous languages.
Dataflow networks: Kahn Process Networks, determinacy and schedulability. Usage examples.
Static scheduling of dataflow networks, minimizing code size or data memory size.
Hardware synthesis of dataflow networks.
Basic real-time scheduling algorithms. Worst-Case Execution Time analysis for software via simulation and formal methods.
Delivery modes

Discussion sessions will reinforce concepts descrive during lessons and apply them to the solution of simple exercises, to be first solved individually and then discussed at the blackboard.
Laboratory sessions will require the use of the SystemC language to model the functionality and performance of an embedded system, including both control-dominated and data-dominated aspects.
Texts, readings, handouts and other learning resources

Peter Marwedel, "Embedded System Design", Kluwer Academic Publishers, 2003.
Maurizio Tranchero and Luciano Lavagno, "Ottimizzazione e modellizzazione di sistemi elettronici", www.lulu.com, 2009 (being translated into English)
Slides used during classes.
Laboratory guide.
Assessment and grading criteria


The exam starts with an open-book written test (about 1 hour), covering the entire subject, followed by an oral exam. The instructor may change this organization to a purely oral exam (if there are only very few students) or to a purely written test (lasting about two hours), with appropriate previous notice.

Programma definitivo per l'A.A.2012/13
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