Politecnico di Torino
Politecnico di Torino
Politecnico di Torino
Academic Year 2015/16
Modeling and optimization of embedded systems
Master of science-level of the Bologna process in Electronic Engineering - Torino
Master of science-level of the Bologna process in Computer Engineering - Torino
Teacher Status SSD Les Ex Lab Years teaching
Lavagno Luciano ORARIO RICEVIMENTO PO ING-INF/01 48 0 12 7
SSD CFU Activities Area context
ING-INF/01 6 C - Affini o integrative Attivitΰ formative affini o integrative
ORA-01722: invalid number
Subject fundamentals
The course is taught in English.
This course introduces the main mathematical models and methods used for the synthesis and verification of embedded hardware and software. It assumes a good knowledge of digital hardware design (with VHDL or Verilog) and of software implementation (with C, C++ or Java) for embedded systems, including a basic knowledge of real-time operating systems. It provides the ability to select and use the best tools and methods for hardware/software co-design, as well as simulation and performance analysis. It provides knowledge about the SystemC language, synchronous languages and dataflow networks.
Expected learning outcomes
• Knowledge of the main formal models and specification languages based on extended finite state machines and dataflow networks.
• Knowledge of the hardware and software synthesis methods for synchronous languages and dataflow networks.
• Knowledge of embedded software performance analysis techniques.
• Ability to analyze at a high level the computational and communication requirements of an embedded application.
• Ability to select the best specification languages and implementation tools, and to select a hardware/software architecture for an embedded system.
• Ability to create a simulation model of an embedded system using a modeling language (e.g. SystemC).
Prerequisites / Assumed knowledge
• Digital hardware design using Verilog or VHDL
• C, C++ or Java programming
• Architecture of at least one CPU, memory architecture and micro-controller.
• Micro-controller peripheral programming.
• Elements of real-time schedulability theory.
Topics (about 1/2 credit each):
• Characteristics of embedded systems, architectures and design flows.
• Control-dominated systems and data-dominated systems.
• SystemC language: syntax and semantics. Usage examples.
• SystemC design at Transaction level (TLM) and Register Transfer Level (RTL).
• Extended Finite State machines. Synchronous (Moore and Mealy) and asynchronous composition.
• Synchronous languages: StateCharts, Esterel and ECL. Control constructs (emit, await, abort, parallel). Usage examples.
• Hardware and software synthesis techniques for Esterel. Interfacing methods with operating systems and peripherals.
• Formal property verification (liveness and safety) using synchronous languages.
• Dataflow networks: Kahn Process Networks, determinacy and schedulability. Usage examples.
• Static scheduling of dataflow networks, minimizing code size or data memory size.
• Hardware synthesis of dataflow networks.
• Basic real-time scheduling algorithms. Worst-Case Execution Time analysis for software via simulation and formal methods.