Politecnico di Torino
Politecnico di Torino
Politecnico di Torino
Anno Accademico 2017/18
Testing and fault tolerance
Corso di Laurea Magistrale in Ingegneria Informatica (Computer Engineering) - Torino
Corso di Laurea Magistrale in Ingegneria Elettronica (Electronic Engineering) - Torino
Corso di Laurea Magistrale in Mechatronic Engineering (Ingegneria Meccatronica) - Torino
Docente Qualifica Settore Lez Es Lab Tut Anni incarico
Sonza Reorda Matteo ORARIO RICEVIMENTO PO ING-INF/05 40 10 10 0 6
SSD CFU Attivita' formative Ambiti disciplinari
ING-INF/05 6 B - Caratterizzanti Ingegneria informatica
The course introduces methods and techniques for the test of electronic circuits and systems, i.e., for detecting the presence of possible faults affecting the target product. Special emphasis is devoted to the test of faults affecting the hardware components.
Risultati di apprendimento attesi
Knowledge of the concept of testing and dependability.
- Knowledge of the main techniques used for testing a digital circuit.
- Knowledge of the main techniques used for testing an embedded system.
- Capability of developing the test plan for a digital device or embedded system
- Capability to use the main software tools for testing an embedded system: fault simulators, automatic test pattern generators, automatic scan chain inserters.
- Knowledge of the concept of Built-In Self-Test (BIST) and Boundary Scan (BS)
- Capability of designing BIST hardware modules.
Prerequisiti / Conoscenze pregresse
The course is better followed if the student owns the knowledge about
Digital system design
1. Introduction to test and dependability (1 credit)
a. Dependability: definition, attributes
b. Fault models (temporary and transient): stuck-at, bridge, open, delay, SEU, SET
c. Test of ICs, boards and systems
d. Defect level: definition and evaluation
e. ATEs
2. Techniques and tools for generating test stimuli for combinational and sequential modules (1 credit)
a. Fault simulation
b. Automatic Test Pattern Generation
3. Techniques and tools for testing specific modules (1 credit)
a. Memory test
b. Processor test
4. Design for Testability techniques (1 credit)
a. Scan
c. Boundary Scan
d. System on Chip test (IEEE 1500 and 1687)
5. Board test (0.5 credit)
a. Main steps in PCB test
b. IEEE 1149.1
6. Basics in fault tolerant system design (1.5 credits)
a. Basic fault tolerant design solutions (hw redundancy, information redundancy, time redundancy)
b. Reliability evaluation (FMEA, radiation experiments, fault injection)
Organizzazione dell'insegnamento
Laboratory activities are an integral part of this course. During the lab sessions students will face the practical aspects introduced by lectures. Lab sessions will allow students to work with commercial tools for Fault Simulation, Scan Insertion and Automatic Test Pattern Generation. Students will also be asked to develop assignments concerning the course subjects.
Testi richiesti o raccomandati: letture, dispense, altro materiale didattico
Students may benefit of the following textbook:

M. Bushnell, V. Agrawal:
Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits
Kluwer Academic Publisher, 2000

Slides will be provided to students registered to the course through the Student Teaching Portal, as well as any additional non-copyrighted information material that will be used in the course.
Criteri, regole e procedure per l'esame
The exam will be based on a written part in which the students will be asked to answer to some (about 6) questions and exercises. The exam will last for about 90 minutes.
The students will be allowed to make an assignment which could increase the score of the written exam by 0 to 4 points.
If the student achieves at least 18 points in the written exam, he/she may ask for an oral exam.
Orario delle lezioni
Statistiche superamento esami

Programma definitivo per l'A.A.2017/18

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Corso Duca degli Abruzzi, 24 - 10129 Torino, ITALY
WCAG 2.0 (Level AA)