Politecnico di Torino
Politecnico di Torino
Politecnico di Torino
Academic Year 2015/16
Computer architectures
Master of science-level of the Bologna process in Computer Engineering - Torino
Teacher Status SSD Les Ex Lab Tut Years teaching
Mezzalama Marco ORARIO RICEVIMENTO     58 24 18 0 8
SSD CFU Activities Area context
ING-INF/05 10 B - Caratterizzanti Ingegneria informatica
Subject fundamentals

The course is taught in Italian.
Mandatory course for Laurea Magistrale in Computer Science Engineering, didactic period I in the first year of course
The purpose of the course is to provide a basic knowledge on the elaboration system architecture, with a particular attention to microprocessor based sistems. The course analyzes the several components of an elaboration system: from the microprocessor internal architecture, up to system bus for peripheral devices management.
Expected learning outcomes
- Knowledge of several processor architectures, with particular attention paid to x86 and ARM families
- Superscalar and multithread architectures
- Design methodologies to central memory, taking the hierarchies (cache L1, L2) and the manufacturing technologies (DDR3,') into account
- Knowledge about system bus, cpu and I/O characteristics
- Competences about I/O management and interface design
- Microprocessor-based system design ability
- Memory module design ability
- Peripheral component interface design ability
- Assembly code implementation for I/O device management.
Prerequisites / Assumed knowledge
- Knowledge of elaboration systems architecture: processor structure and memory organization
- Knowledge of basic functionalities of operative systems
- Capability to develop programs in assembler language
CISC processor of x86 family architecture (2 credits)
- Classification
- Register architecture
- Internal and external bus architecture
- Management of memory segments and pages
- Real and protected mode

ARM family microprocessor (0.5 credits)
- Register architecture
- Internal and external bus architecture
- Management of memory segments and pages

Memory sub-system architecture (1 credit)
- Cache memory
- Devices and models for RAM memories
- Memory banks design

System bus architectures (1 credit)
- Classes and timing
- Examples: PCI

- Superscalar microprocessor architecture (1 credito)

Management of peripheral devices (1.5 crediti)
- Interrupt, DMA
- Most diffused peripheral architectures (serial port, parallel port, timer)
- Development of software drivers
- Magnetic disks management
Delivery modes
Class exercitations (2 credits)
- Development of program in x86 assembler language
- Development of program in ARM assembler language
- Development of peripheral interfaces
- Design of simple systems

laboratory exercitations (1 credit)
- Development of assembly programs to verify over different platforms
Texts, readings, handouts and other learning resources
-- Prinetto, Rebaudengo, Sonza:
'Il linguaggio di programmazione assembler 8086', Levrotto&Bella
- Irvine:
'Assembly language for intel-based computers', IV ed., Prentice Hall
- Furber:
'ARM: system-on-chip architecture', Addison Wesley

Didactic material available on the WEB
- Slides shown during classes
- Execises
- Video of lessons and exercitations
Books, selected among the itemized, will be indicated by the professors.
Assessment and grading criteria
The exam is constituted by a written prove of two parts:
1. The first part consists in open questions about subjects treated during classes. Along this part it is not allowed to use any book or other material.
2. The second part consists in the development of an assemble program. Along this part it is possible to use books and other material.

In case the written prove is resulting in a mark major or equal to 18/30, it is possible to access to an oral exam about the entire program.

Programma definitivo per l'A.A.2015/16

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Corso Duca degli Abruzzi, 24 - 10129 Torino, ITALY
WCAG 2.0 (Level AA)