Politecnico di Torino
Politecnico di Torino
Politecnico di Torino
Academic Year 2015/16
Computer architectures
Master of science-level of the Bologna process in Computer Engineering - Torino
Teacher Status SSD Les Ex Lab Years teaching
Mezzalama Marco ORARIO RICEVIMENTO PO ING-INF/05 58 0 18 8
SSD CFU Activities Area context
ING-INF/05 10 B - Caratterizzanti Ingegneria informatica
ORA-01722: invalid number
Subject fundamentals

The course is taught in Italian.
Mandatory course for Laurea Magistrale in Computer Science Engineering, didactic period I in the first year of course
The purpose of the course is to provide a basic knowledge on the elaboration system architecture, with a particular attention to microprocessor based sistems. The course analyzes the several components of an elaboration system: from the microprocessor internal architecture, up to system bus for peripheral devices management.
Expected learning outcomes
- Knowledge of several processor architectures, with particular attention paid to x86 and ARM families
- Superscalar and multithread architectures
- Design methodologies to central memory, taking the hierarchies (cache L1, L2) and the manufacturing technologies (DDR3,') into account
- Knowledge about system bus, cpu and I/O characteristics
- Competences about I/O management and interface design
- Microprocessor-based system design ability
- Memory module design ability
- Peripheral component interface design ability
- Assembly code implementation for I/O device management.
Prerequisites / Assumed knowledge
- Knowledge of elaboration systems architecture: processor structure and memory organization
- Knowledge of basic functionalities of operative systems
- Capability to develop programs in assembler language
CISC processor of x86 family architecture (2 credits)
- Classification
- Register architecture
- Internal and external bus architecture
- Management of memory segments and pages
- Real and protected mode

ARM family microprocessor (0.5 credits)
- Register architecture
- Internal and external bus architecture
- Management of memory segments and pages

Memory sub-system architecture (1 credit)
- Cache memory
- Devices and models for RAM memories
- Memory banks design

System bus architectures (1 credit)
- Classes and timing
- Examples: PCI

- Superscalar microprocessor architecture (1 credito)

Management of peripheral devices (1.5 crediti)
- Interrupt, DMA
- Most diffused peripheral architectures (serial port, parallel port, timer)
- Development of software drivers
- Magnetic disks management