Politecnico di Torino
Politecnico di Torino
Politecnico di Torino
Anno Accademico 2013/14
Specification and simulation of digital systems
Corso di Laurea Magistrale in Ingegneria Informatica (Computer Engineering) - Torino
Docente Qualifica Settore Lez Es Lab Anni incarico
Camurati Paolo Enrico ORARIO RICEVIMENTO PO ING-INF/05 40 0 20 11
SSD CFU Attivita' formative Ambiti disciplinari
ING-INF/05 6 B - Caratterizzanti Ingegneria informatica
ORA-01722: invalid number
Course appearing in the tracks Embedded Systems and Software and Digital Systems). Students acquire the skills to describe digital systems at various levels of abstraction with the VHDL language. The course completes the design methodologies acquired in previous basic digital design courses and extends them to the register-transfer level focusing on automated synthesis. The course uses simulation-based verification techniques to develop in a lab a complex design and deals with verification techniques based on formal methods, in particular combinational and sequential equivalence check and model checking. The course introduces the basic knowledge on testing digital circuits.
Risultati di apprendimento attesi
Knowledge of the syntax and semantics of VHDL
Ability to describe complex digital systems in VHDL at various levels of abstraction
Knowledge of the fundamental features of embedded systems
Knowledge of the metrics to evaluate designs
Knowledge of the design methodologies for register-transfer level systems
Ability to design complex digital systems at the register-transfer level with CAD tools
Ability to verify by simulation complex digital system designs
Knowledge of the main formal verification techniques with particular emphasis on combinational and sequential equivalence check and model checking
Knowledge of the fundamental notions in testing
Ability to generate test patterns for simple combinational circuits
Prerequisiti / Conoscenze pregresse
Knowledge of basic design techniques for combinational and synchronous sequential circuits.
VHDL: structure of VHDL files: entity/architecture; description styles: behavioral, dataflow, structural; lexical elements; objects: signals, variables and constants; data types: scalar types, composite types; operators and attributes; concurrent statements: concurrent signal assignments, generate statements, concurrent processes, component instantiations; sequential statements: processes, conditional statements, iterative statements; partitioning techniques: blocks, packages, libraries, components, configurations. Examples of combinational, synchronous and basic register-transfer level designs in VHDL.
Register Transfer-level embedded systems design: design metrics and their optimization; key technologies for embedded systems: processor technology, IC technology, design technology; single-purpose processor design: the FSM-D model, from the algorithm to the FSM-D, synthesis of the datapath, synthesis of the control unit, description in VHDL; optimization of single-purpose processors: algorithm, FSM-D, datapath, FSM; optimization of Finite State Machines (FSMs): state minimization (simplified and exact equivalent state detection algorithm), state encoding heuristics.
RT-level system design: execution graphs (concurrent, sequential, group-sequential); system organization (shared systems, non-shared systems, single-module systems); centralized vs decentralized vs partially centralized control; specification and implementation in VHDL of RT-level systems; design methodology for RT-level systems.
Data and control subsystems: components and organization of data subsystems; data subsystems design; implementation of control subsystems as FSMs.
Formal verification: approaches to design verification: simulation vs. formal verification; theorem proving: propositional logic, first-order logic, higher-order logic; equivalence checking: Binary Decision Diagrams, combinational equivalence check, sequential equivalence check (symbolic reachability analysis, the product machine model); Model Checking: linear-time temporal logic, branching-time temporal logic, liveness and safety properties, model checking algorithms.
Principles of electronic testing: physical failures and fault models; the stuck-at fault model: fault detection, fault equivalence and collapsing, fault coverage); algorithms for test pattern generation (Boolean difference).