Politecnico di Torino
Politecnico di Torino
Politecnico di Torino
Academic Year 2017/18
Specification and simulation of digital systems
Master of science-level of the Bologna process in Computer Engineering - Torino
Teacher Status SSD Les Ex Lab Tut Years teaching
Camurati Paolo Enrico ORARIO RICEVIMENTO PO ING-INF/05 42 0 18 80 15
SSD CFU Activities Area context
ING-INF/05 6 B - Caratterizzanti Ingegneria informatica
Subject fundamentals
Course appearing in the tracks Embedded Systems and Software and Digital Systems). Students acquire the skills to describe digital systems at various levels of abstraction with the VHDL language. The course completes the design methodologies acquired in previous basic digital design courses and extends them to the register-transfer level focusing on automated synthesis. The course uses simulation-based verification techniques to develop in a lab a complex design and deals with verification techniques based on formal methods, in particular combinational and sequential equivalence check and model checking. The course introduces the basic knowledge on testing digital circuits.
Expected learning outcomes
• Knowledge of the syntax and semantics of VHDL
• Ability to describe complex digital systems in VHDL at various levels of abstraction
• Knowledge of the fundamental features of embedded systems
• Knowledge of the metrics to evaluate designs
• Knowledge of the design methodologies for register-transfer level systems
• Ability to design complex digital systems at the register-transfer level with CAD tools
• Ability to verify by simulation complex digital system designs
• Knowledge of the main formal verification techniques with particular emphasis on combinational and sequential equivalence check and model checking
• Knowledge of the fundamental notions in testing
• Ability to generate test patterns for simple combinational circuits
Prerequisites / Assumed knowledge
Knowledge of basic design techniques for combinational and synchronous sequential circuits.
• VHDL: structure of VHDL files: entity/architecture; description styles: behavioral, dataflow, structural; lexical elements; objects: signals, variables and constants; data types: scalar types, composite types; operators and attributes; concurrent statements: concurrent signal assignments, generate statements, concurrent processes, component instantiations; sequential statements: processes, conditional statements, iterative statements; partitioning techniques: blocks, packages, libraries, components, configurations. Examples of combinational, synchronous and basic register-transfer level designs in VHDL.
• Register Transfer-level embedded systems design: design metrics and their optimization; key technologies for embedded systems: processor technology, IC technology, design technology; single-purpose processor design: the FSM-D model, from the algorithm to the FSM-D, synthesis of the datapath, synthesis of the control unit, description in VHDL; optimization of single-purpose processors: algorithm, FSM-D, datapath, FSM; optimization of Finite State Machines (FSMs): state minimization (simplified and exact equivalent state detection algorithm), state encoding heuristics.
• RT-level system design: execution graphs (concurrent, sequential, group-sequential); system organization (shared systems, non-shared systems, single-module systems); centralized vs decentralized vs partially centralized control; specification and implementation in VHDL of RT-level systems; design methodology for RT-level systems.
• Data and control subsystems: components and organization of data subsystems; data subsystems design; implementation of control subsystems as FSMs.
• Formal verification: approaches to design verification: simulation vs. formal verification; theorem proving: propositional logic, first-order logic, higher-order logic; equivalence checking: Binary Decision Diagrams, combinational equivalence check, sequential equivalence check (symbolic reachability analysis, the product machine model); Model Checking: linear-time temporal logic, branching-time temporal logic, liveness and safety properties, model checking algorithms.
• Principles of electronic testing: physical failures and fault models; the stuck-at fault model: fault detection, fault equivalence and collapsing, fault coverage); algorithms for test pattern generation (Boolean difference).
Delivery modes
Lectures (40h) covering the syllabus + 20h lab work: students work with the Xilinxฎ ISE' 11 package to develop a RT-level design according to the methodologies described in the lectures. The design is evaluated on the CoolRunnerTM-II Evaluation Board, a complete USB-powered circuit development platform for the Xilinx CoolRunner-II CPLD (2.0 cr).
Texts, readings, handouts and other learning resources
Handouts published on the course site.

Additional readings:
• F. Vahid, "Digital Design with RTL design, VHDL and Verilog", 2nd edition, John Wiley, 2010
• D. Pellerin, D. Taylor "VHDL Made easy!", Prentice Hall 1997
• F. Vahid, T. Givargis "Embedded System Design: a unified hardware/software introduction", John Wiley, 2002
• M.Ercegovac, T. Lang, J. Moreno "Introduction to digital systems", John Wiley, 1999
• S. Mourad, Y. Zorian "Principles of Testing Electronic Systems", John Wiley, 2000 '
• ISE in-depth tutorial, Xilinx
• CoolRunner-II Evaluation Board Reference Manual, Xilinx
Assessment and grading criteria
A homework is assigned to each group of 2/3 students during the last part of the course. It consists of a RT-level design of a complex systems described in VHDL. The design activity starts in the lab during the course, then the students complete it. The homework is ranked. If the mark is sufficient, follows an oral exam on all the topics dealt with during the course. The final mark takes into account both the homework and the oral exam.

Programma definitivo per l'A.A.2017/18

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