This course is taught in English.

The aim of the module is to learn to analyze and design circuits that are the base of today's electronic analog and digital systems. Building on the foundations provided by previous courses of electrical engineering, electronic devices and circuits, the operational amplifiers are first introduced and used in linear and nonlinear applications. The second topic covers linear and switching power supplies. Then we study the basic modes of operation of switching transistors and use them to analyze the structure of logic gates. The analysis of data acquisition systems completes the module.

Become familiar with analog electronics and electrical aspects of digital electronics.
Design small analog systems from specifications.
Design simple power supplies for electronic circuits.
Design a digital circuit and the interface between it and a load.
Understand the classic data acquisition systems and know how to design then from specifications.

he student must know the theory of electrical networks, their time domain frequency domain analysis, the operation in the linear region of bipolar transistors and MOS, the concept of bias and small signal. He/she also needs to know the basic concepts of signal theory and feedback. As for the experimental exercises, the student should have gained some familiarity in using laboratory equipment (oscilloscope, power supply, signal generator).

Operational amplifiers (4 CFU)
- structure of operational amplifiers with BJT and MOS: current mirror, differential stage, power stage. Power amplifiers with discrete components
- Parasitic parameters of operational amplifiers, frequency response, stability
- Linear circuits: amplifier, adder, instrumentation amplifier
- Active filters: first order, second order, higher order; switched capacitor filter
- Non-linear circuits: logarithmic amplifier, ideal diode
- Threshold comparators, waveform generators, VCO
- Sinusoidal oscillators: the Wien bridge, phase shift oscillator, three-point
'
Power supplies (1,5 CFU)
- Traditional structure with dissipative controller
- Switching regulator

Logic gates and switching circuits (2 CFU)
- Bipolar and MOS switching transistors, switches, transmission gates, CMOS gates
- Static and dynamic parameters of logic families, open drain and tri-state outputs, Schmitt trigger inputs
- Interfacing with loads and optical isolation
- And-Or-Invert ports, dynamic logic
- Basic sequential circuits (latches, flip-flops, counter); dynamic behavior

Data Acquisition Systems (1 CFU)
- Elements of sampling theory, quantization; D / A converter (potentiometric, weighted resistors, R-2R ladder); A / D converter (flash, successive approximation, tracking); Sample & Hold (integrating)

The course includes 8 two hours (1,5 CFU) experimental laboratory exercises to be performed at the LED. The labs are organized in groups of three or four students. For each lab group must prepare reports that are evaluated by the instructor and constitute part of final examination mark.
1. Operational amplifier characteristics;
2. Active filter;
3. Instrumentation amplifier;
4. Triangular wave generator;
5. Dissipative voltage regulator;
6. Switching converter;
7. Characteristics of logic gates;
8. D / A converter

Several lecture notes in Italian covering almost the entire contents of the module are available on the official Politecnico website, where it is also possible to download the specs of the experimental exercises. For further details and discussions the recommended text is: Sedra / Smith, "Microelectronic Circuits", 5th ed. Oxford University Press. ISBN 0-19-514252-7

The examination consists of an oral test (two questions) preceded by a written exercise (time available: 30') which is corrected at the beginning of the oral test. The mark obtained in the written exercise and oral requests accounts for 80% of the final examination mark. The remaining 20% derives from the average of the evaluations of the reports of experimental exercises. This average is calculated on the best six reports of each student. If the student has made less than six reports, the missing reports are mediated by the value 0 / 30.