Politecnico di Torino
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Politecnico di Torino
Anno Accademico 2014/15
02NPBOV, 02NPBOQ
Testing
Corso di Laurea Magistrale in Ingegneria Informatica (Computer Engineering) - Torino
Corso di Laurea Magistrale in Ingegneria Elettronica (Electronic Engineering) - Torino
Docente Qualifica Settore Lez Es Lab Anni incarico
Sonza Reorda Matteo ORARIO RICEVIMENTO PO ING-INF/05 40 10 10 5
SSD CFU Attivita' formative Ambiti disciplinari
ING-INF/05
ING-INF/05
4
2
B - Caratterizzanti
F - Altre (art. 10, comma 1, lettera f)
Ingegneria informatica
Abilità informatiche e telematiche
Precedenze:
02LVN
Presentazione
The course introduces methods and techniques for the test of electronic circuits and systems, i.e., for detecting the presence of possible faults affecting the target product. Special emphasis is devoted to the test of faults affecting the hardware components.
Risultati di apprendimento attesi
- Knowledge of the concept of testing and dependability.
- Knowledge of the main techniques used for testing a digital circuit.
- Knowledge of the main techniques used for testing an embedded system.
- Capability of developing the test plan for a digital device or embedded system
- Capability to use the main software tools for testing an embedded system: fault simulators, automatic test pattern generators, automatic scan chain inserters.
- Knowledge of the concept of Built-In Self-Test (BIST) and Boundary Scan (BS)
- Capability of designing BIST hardware modules.
Prerequisiti / Conoscenze pregresse
The course is better followed if the student owns the knowledge about
• Digital system design
• Microelectronics.
Programma
Introduction to test and dependability (1 credit)
Techniques and tools for generating test stimuli for combinational and sequential circuits (1 credit)
Techniques and tools for testing specific devices (e.g., memories and processors) (1 credit)
Design for Testability techniques: scan, BIST, Boundary Scan (2 credits)
Basics in fault tolerant system design (1 credit)
Organizzazione dell'insegnamento
Laboratory activities are an integral part of this course. During the lab sessions students will face the practical aspects introduced by lectures. Lab sessions will allow students to work with commercial tools for Fault Simulation, Scan Insertion and Automatic Test Pattern Generation. Students will also be asked to develop assignments concerning the course subjects.
Testi richiesti o raccomandati: letture, dispense, altro materiale didattico
Students may benefit of the following textbook:

M. Bushnell, V. Agrawal:
Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits
Kluwer Academic Publisher, 2000

Slides will be provided to students registered to the course through the Student Teaching Portal, as well as any additional non-copyrighted information material that will be used in the course.
Criteri, regole e procedure per l'esame
The exam will be based on a written part in which the students will be asked to answer to some (about 6) questions and exercises. The exam will last for about 90 minutes.
The students will be allowed to make an assignment which could increase the score of the written exam by 0 to 4 points.
If the student achieves at least 18 points in the written exam, he/she may ask for an oral exam.
Orario delle lezioni
Statistiche superamento esami

Programma definitivo per l'A.A.2014/15
Indietro



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