Politecnico di Torino
Politecnico di Torino
   
Login  
it
Politecnico di Torino
Academic Year 2017/18
02NVPBG
Programmable electronic systems
Master of science-level of the Bologna process in Communications And Computer Networks Engineering - Torino
Teacher Status SSD Les Ex Lab Tut Years teaching
Casu Mario Roberto ORARIO RICEVIMENTO A2 ING-INF/01 40 10 30 0 7
SSD CFU Activities Area context
ING-INF/01 8 D - A scelta dello studente A scelta dello studente
Esclusioni:
01RLI; 03LPX
Subject fundamentals
The course entitled Programmable Electronic Systems is offered to those students who intend to deepen their skills in the design of digital electronic systems, even of large complexity, to be implemented by means of programmable platforms. Methodological aspects are covered and paired with the analysis of practical topics, which encompass experimental activities, examples and case studies.
Expected learning outcomes
The course enables students to acquire the knowledge and ability to apply design techniques for digital systems in general and to investigate in particular aspects concerning the implementation with programmable platforms. Accordingly, the examination at the end of the learning module will ensure that the student has learned the following:
- Knowledge of methods to describe, simulate and analyze the behavior of a digital system.
- Skill in using computer-based methods for description, simulation and analysis of even complex systems.
- Knowledge of typical structure and technology of modern programmable electronic components.
- Knowledge of design flow on programmable systems.
- Ability to design a digital electronic system from specifications to implementation and to experimental verification of the behavior.
Ability to draft a technical report on the design and characterization of a component or digital electronic system.
Prerequisites / Assumed knowledge
Studentsí prerequisites are: basic knowledge of Boolean Algebra, logic gates, combinational and sequential elementary components, ability in analyzing simple digital circuits.
Contents
Class lectures will cover the following topics:
- Design methodologies of digital systems implemented on programmable electronics systems and described with VHDL hardware-description language (1.8 credits).
- Technologies and architectures of programmable electronic systems, basic components, design flow, programmable systems-on-chip (1.8 credits).
- Examples of applications (0.4 credits).
Delivery modes
Seven laboratories complete studentsí training, three hours each (about 2 credits). Experiments will be conducted by students organized in groups of 3-4 people who will work on projects from the conception phase all the way down to the implementation on a programmable logic device. The phases through which students will go are: specification, functional simulation, logic synthesis, floorplanning, place and route, post-routing simulation, programming file generation, experimental verification of correctness. A technical report is drawn up by each group in each laboratory session. Reports have to be delivered no more than one week after the date of the laboratory. Reports are graded, and the obtained mark contributes to the final mark of the exam (weight: 0.35). Reports not delivered are graded with mark zero.
Texts, readings, handouts and other learning resources
Handouts, slides and other teaching material used during classes are available through the course website. No single textbook covers the whole program, but the following books are suggested for further individual study:

- S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design, McGraw-Hill Higher Education (available in the library)
- P. Chu, RTL Hardware Design using VHDL, John Wiley & Sons
- C. Maxfield, The Design Warrior's Guide to FPGAs, Elsevier
- P. Chu, Embedded SoPC Design with Nios II Processor and VHDL Examples, John Wiley & Son
Assessment and grading criteria
The final exam consists of a written test that lasts two hours. The students are not allowed to use any teaching material during the exam. The written test consists of three parts, each weighted approximately 1/3: one exercise of VHDL description of a hardware component; one open-ended question about design methodologies, technologies, architectures, design flow, or systems-on-chip in programmable systems; 5 multiple-choice questions about all course topics (penalty in case of wrong answer, no penalty for question unanswered). Final mark is an average of written test (weighted by 0.65) and the mark obtained for labs technical reports (weighted by 0.35).

Programma definitivo per l'A.A.2017/18
Back



© Politecnico di Torino
Corso Duca degli Abruzzi, 24 - 10129 Torino, ITALY
WCAG 2.0 (Level AA)
Contatti