| KEYWORD |
GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA
Cycle-estimation through Just-in-time-compilation in MLIR
Thesis abroad
keywords COMPILER, HETEROGENEOUS HARDWARE, GPU, FPGA, EMBED, COMPILERS, DEEP NEURAL NETWORKS, EMBEDDED SYSTEMS, ENERGY EFFICIENCY, LOW POWER, MICROCONTROLLERS, SOFTWARE
Reference persons ALESSIO BURRELLO, DANIELE JAHIER PAGLIARI
External reference persons Prof. Marian Verhelst (KU Leuven)
Dr. Josse Van Delm (KU Leuven)
Research Groups DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA, ELECTRONIC DESIGN AUTOMATION - EDA, GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA
Thesis type EMBEDDED SOFTWARE DEVELOPMENT, EXPERIMENTAL, RESEARCH, SOFTWARE DEVELOPMENT
Description Performance analysis on heterogeneous systems is challenging due to the wide variety of software and hardware involved. While many different levels of modeling exist to trade off cycle count estimates precision for execution speed, these methods all require adding extra modeling capabilities to be added, which prohibits scaling in the case of many heterogeneous systems or sometimes does not allow for dynamic workload simulation.
In this master thesis, we propose a novel method based on MLIR to perform semi-static code analysis to get accurate performance counts at various levels of code involvement and precision. Due to the integrated nature of this method, it immediately scales with increasing compiler capabilities and can produce high-performance code to assess performance.
The master thesis student will construct a JIT-compiler-based SNAX framework cycle-count estimator, that is based on SNAX-MLIR, which is based on the MLIR-compatible xDSL framework, and is expected to profile the accuracy and simulation speed of the proposed method w.r.t. cycle-accurate simulators like verilator.
Interesting related work:
https://dl.acm.org/doi/pdf/10.1145/1403375.1403380
https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9251937&tag=1
Required skills Thorough knowledge of Python and RISC-V, Interest in optimizing compilers and microarchitecture performance analysis. Knowledge about neural networks and accelerators is considered a strong plus.
Notes Thesis in collaboration with Prof. Marian Verhelst’s research group at KU Leuven. The thesis can be carried out either in Torino or in Lueven (with a strong preference to carry it out at Leuven).
Deadline 06/11/2025
PROPONI LA TUA CANDIDATURA