| KEYWORD |
Microelectronics
FPGA-based acceleration of subgraph isomorphism
keywords FPGA ACCELERATION, GRAPHS, HIGH-LEVEL SYNTHESIS
Reference persons LUCIANO LAVAGNO
External reference persons Roberto Bosio
Research Groups Microelectronics
Thesis type RESEARCH
Description Graph processing has become an integral part of various areas, such as machine learning, medical applications, and social network analysis.
In instances like web or social networks, graphs can reach trillions of edges, presenting a significant challenge due to their vast scale and non-uniform nature.
Field Programmable Gate Arrays (FPGAs) can be an energy-efficient solution to deliver specialized hardware for graph processing.
The thesis aims to address the computational challenges associated with graph algorithms acceleration, specifically the subgraph isomorphism problem, a fundamental problem in graph theory.
The accelerator aims to enhance the performance of an existent subgraph isomorphism solver, by optimizing the data movement from/to memory for dedicated data center FPGAs.
Required skills - FPGA design
- C/C++ coding
- high-level synthesis is desireable but not mandatory
Deadline 16/01/2025
PROPONI LA TUA CANDIDATURA