| KEYWORD |
Microelectronics
Deep neural network synthesis for FPGAs via high-level synthesis
Tesi esterna in azienda 
Tesi all'estero
Parole chiave HIGH-LEVEL SYNTHESIS, MACHINE LEARNING
Riferimenti LUCIANO LAVAGNO, MIHAI TEODOR LAZARESCU
Riferimenti esterni Fabian Chersi, CEA Paris Saclay
Gruppi di ricerca Microelectronics
Descrizione The goal of the thesis is to prototype and test the code generation capabilities of the AIdge ML deployment framework for FPGAs.
The tasks will be:
- select a suitable CNN for the experiment (perhaps Resnet20)
- define a list of layers that need to be supported (probably 2-3)
- write the c++ code implementing the layers (probably about 1000 lines of code)
- use the generated code in Vitis HLS and analyze the results
Conoscenze richieste C/C++
Digital HW design
Knowledge of HLS is preferred
Note The thesis can be carried out at CEA Saclay or at Politecnico di Torino, under the guidance of both groups, based on the student's preferences
Scadenza validita proposta 31/10/2025
PROPONI LA TUA CANDIDATURA