| KEYWORD |
DAUIN - GR-13 - METODI FORMALI - FM
ARMADA: A Framework for Automatic Hardware Design Debugging and Repair
Thesis in external company 
Thesis abroad
keywords RTL DEBUGGING; EXPLAINABLE AI; PROGRAM REPAIR; LAR
Reference persons STEFANO QUER
External reference persons Debjit Pal, University of Illinois Chicago, IL, USA
Research Groups DAUIN - GR-13 - METODI FORMALI - FM
Thesis type RESEARCH / EXPERIMENTAL
Description Overview
In recent years, there has been an exponential growth in the size and complexity of System-on-Chip (SoC) designs targeting different specialized applications. The cost of an undetected bug in these systems is much higher than in traditional processor systems, as it may imply the loss of property or life. The problem is further exacerbated by the ever-shrinking time-to-market and ever-increasing design complexity and demand to churn out billions of hardware devices. Despite decades of research in simulation and formal methods for debugging and verifying pre-silicon register transfer level (RTL) design, RTL debugging is still one of the most time-consuming and resource-intensive processes in the contemporary hardware design cycle. Current industrial practice primarily uses regression techniques and what-if analysis for debugging. However, such methods are extremely time-consuming and often rely on deep insights from human experts. On the other hand, academic researchers have proposed automated debugging techniques using data-driven statistical analysis, SAT, and BDD. However, such methods often suffer from scalability issues, do not provide human-comprehensible explanations of failure root causes, and do not automatically create code patches to fix buggy designs. This project will address this critical problem by creating ARMADA, a new foundational infrastructure, and a comprehensive tool suite for pre-silicon RTL debugging. A critical insight is that recent advances in state-of-the-art deep learning models, such as Transformer, Large Language Models (LLMs), have enormous potential to root cause and localize, explain root causes that are human understandable, and generate code patches to debug the RTL designs. We propose integrating this insight in ARMADA to create a novel, scalable, and effective pre-silicon debugging and repairing framework.
Intellectual Merit
The project will develop a unified foundational infrastructure and comprehensive suite of tools to enable streamlined pre-silicon RTL debugging and repairing of realistic SoCs.
(1) It will develop novel technologies for characterizing and classifying design failure traces for effective debugging and root cause analysis.
(2) It will create a framework for automatically localizing suspicious design components and design source codes.
(3) It will develop a framework to generate human-understandable explanations of design failures at different abstractions in natural language.
(4) It will develop novel technologies to automatically generate fixes, i.e., code patches to repair suspicious design components. The proposed approaches will be demonstrated on complex, realistic, industry-scale SoC designs.
Required skills Advanced programming skills, basics of data analytics, computer architectures, testing and verification of hardware devices.
Notes The thesis is expected to be carried out under the tutelage of Prof. Debjit Pal at the University of Illinois at Chicago. Visa paperwork will be handled by the University of Chicago offices. All other expenses will be borne by the student. In case of particular impediments, the thesis can be developed at Politecnico.
Deadline 31/03/2024
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