| KEYWORD |
DAUIN - GR-24 - SMILIES - reSilient coMputer archItectures and LIfE Sci
Porting of a hardware accelerator for Spiking Neural Networks and its software driver on a Xilinx PynQ board for edge applications.
keywords ARTIFICIAL INTELLIGENCE, DRIVER, EDGE COMPUTING, FPGA ACCELERATION, HARDWARE ACCELERATORS, NEURAL NETWORKS, NEUROMORPHIC ACCELERATORS, SPIKING NEURAL NETWORKS
Reference persons STEFANO DI CARLO, ALESSANDRO SAVINO
External reference persons CARPEGNA ALESSIO
Research Groups DAUIN - GR-24 - SMILIES - reSilient coMputer archItectures and LIfE Sci
Thesis type APPLIED, APPLIED, EXPERIMENTAL, EXPERIMENTAL - DEVELOPMENT
Description The cloud-computing paradigm, in which a high-performance central elaboration system is used to process data that are collected by small spread devices, has a lot of drawbacks. The high-power consumption, the unpredictable communication latency, the privacy violations given by the transmission of delicate data to a remote machine and so on.
A possible solution consists in moving the data processing, or part of it, directly onto the spread devices. This is called edge computing, to indicate the relocation of the elaboration towards the edge of the system, where the center is represented by the high-performance servers.
The main challenge with this kind of solution is given by the much smaller resources available on edge devices, generally microcontrollers and mobile devices. The design of dedicated hardware accelerators, or co-processors, able to perform a specific task in a very optimized way and to unburden the CPU or MCU of some computational load, can help in such a situation.
The goal of the thesis is the porting of a hardware accelerator for a Spiking Neural Network, together with the software driver required to interface it, both already existing, onto a Xilinx PynQ board. The goal is to test the accelerator on an embedded board with limited resources, evaluating the performance differences with respect to a software simulation of the same network.
Extra
Extensive simulation of the accelerator to evaluate power consumption and area occupation with different network architectures.
Required skills Mandatory: hardware, design VHDL, C programming
Optional: operating systems, C driver development
Deadline 25/10/2023
PROPONI LA TUA CANDIDATURA