GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA
PPACT Evaluation of a Vector Functional Unit
Thesis in external company Thesis abroad
keywords AI HARDWARE, ARM, C, COMPILERS, DEEP LEARNING, DESIGN SPACE EXPLORATION, EMBEDDED SYSTEMS, ENERGY EFFICIENCY, FIRMWARE, HARDWARE AND SOFTWARE, HARDWARE DESIGN, HETEROGENEOUS COMPUTING, LOW POWER, MICROCONTROLLERS, VECTOR PROCESSING
Reference persons DANIELE JAHIER PAGLIARI
External reference persons Yukai Chen (IMEC)
Thesis type EXPERIMENTAL, HARDWARE DESIGN, SOFTWARE DEVELOPMENT
Description This thesis will be carried out at the IMEC research center in Leuven, Belgium.
Addressing the challenges of the scaling wall, memory wall, power wall, and cost wall in Integrated Circuits (ICs) design requires high-density, cost-effective systems that optimize Power, Performance, Area, Cost, and Temperature (PPACT). This can only be achieved by viewing these challenges from a system-level perspective.
During this thesis, the candidate will have the unique opportunity to shape and explore potential computing architectures suitable for future technologies. The primary task will be the RTL (Register-Transfer Level) design of a Vector Functional Unit (VFU) for a wide vector processor to boost high-performance SIMD (Single Instruction, Multiple Data) executions. The task also involves implementing data communication channels for the VFU, which includes designing a very wide register, a tile shuffler, and river routers to establish a robust data communication network capable of clustering VFUs. Finally, generate a broadly usable RTL block netlist of VFU and its communication channels.
Further, the candidate will be required to conduct RTL simulations using real workloads, such as deep learning inference, and perform power and thermal analysis at Gate level. This valuable hands-on experience will allow the student to better understand the intricacies of semiconductor technology and its challenges. Throughout this thesis, the candidate will work closely with a team of system architects and PPACT researchers at IMEC. This collaboration will offer the chance to evaluate your implementation in conjunction with future technology trends and research.
Required skills Candidates should have a background in Electronic/Computer Engineering, with a strong understanding of Computer Architecture, Microarchitecture/ISA. Proficiency in C, Python, SystemVerilog/VHDL, and RTL simulation is necessary.
Notes Thesis carried out at the IMEC research center in Leuven, Belgium, under the supervision of Dr. Francky Catthoor, Dr. Yukai Chen, and Dr. Dwaipayan Biswas. The candidate will be financially supported by IMEC for the travel (around 800/1000 Euro per month, not considering potential scholarships).
Deadline 04/10/2024 PROPONI LA TUA CANDIDATURA