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GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA

Testing SystemVerilog Drivers with Verilator and Google Test: A Framework for Unit Testing in ARM

azienda Thesis in external company    estero Thesis abroad


keywords CPU, SYSTEM VERILOG, SYSTEM VERILOG DRIVERS, VERIFICATION

Reference persons ALESSIO BURRELLO

External reference persons ARM External Supervisor

Research Groups DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA, ELECTRONIC DESIGN AUTOMATION - EDA, GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA

Thesis type EXPERIMENTAL, VERIFICATION

Description In ARM, we face multiple issues while developing the TB with our drivers. It is very complicated to test them without running the whole simulation. Therefore, we would like the following properties:
• We would like to be able to run utest on them without running the whole simulation. A first approach was tried at CoreTB using the SVUnit library. However, SVUnit is not the best, for several reasons, including that wrapping our own verification library around is not easy.
• We would like to investigate the use of Verilator + Gtest to test drivers. (https://github.com/mortenjc/systemverilog) to develop our own utest library around Gtest.
Different steps of the thesis might look like this:
• Compile the drivers using Verilator, it might involve small changes in our SystemVerilog drivers to make them fit with Verilator transpiler.
• Drive signals to run the drivers alone
• Import Gtest to the project and develop a small test to check that Gtest + the transpiled drivers are working correctly together
• Develop a small framework around Gtest in order to make the development of new Utest easy.

Required skills • Software skills, basic C++ (OOP), python experience is a good plus
• HDL experience is good to be able to understand how works the driver we want to transpile to C++

Notes Thesis in collaboration with ARM. The thesis will be done at the Sophia Antipolis site. https://www.arm.com/


Deadline 03/02/2026      PROPONI LA TUA CANDIDATURA