| KEYWORD |
Microelectronics
Verification at STM using Universal Verification Methodology
Thesis in external company
keywords FUNCTIONAL VERIFICATION, UNIVERSAL VERIFICATION METHODOLOGY
Reference persons LUCIANO LAVAGNO
External reference persons Giovanni Auditore, STM Catania
Research Groups Microelectronics
Thesis type RICERCA
Description The thesis will be done at STM Catania. The goal is to develop UVM models and verification suites for various IP blocks including, for example:
- Non-Volatile memories
- ARM bus protocols (AMBA)
- Multi-clock designs
Required skills The student should have knowledge of:
- Digital electronic design
- Computer architecture
- Object-oriented programming
Deadline 07/03/2025
PROPONI LA TUA CANDIDATURA