| KEYWORD |
Microelectronics
Verification at STM using Universal Verification Methodology
Tesi esterna in azienda
Parole chiave FUNCTIONAL VERIFICATION, UNIVERSAL VERIFICATION METHODOLOGY
Riferimenti LUCIANO LAVAGNO
Riferimenti esterni Giovanni Auditore, STM Catania
Gruppi di ricerca Microelectronics
Tipo tesi RICERCA
Descrizione The thesis will be done at STM Catania. The goal is to develop UVM models and verification suites for various IP blocks including, for example:
- Non-Volatile memories
- ARM bus protocols (AMBA)
- Multi-clock designs
Conoscenze richieste The student should have knowledge of:
- Digital electronic design
- Computer architecture
- Object-oriented programming
Scadenza validita proposta 07/03/2025
PROPONI LA TUA CANDIDATURA