| KEYWORD |
Microelectronics
Artificial Intelligence-assisted coverage closure for functional hardware verification
Thesis in external company
keywords FUNCTIONAL VERIFICATION, MACHINE LEARNING, UNIVERSAL VERIFICATION METHODOLOGY
Reference persons LUCIANO LAVAGNO
External reference persons Giovanni Auditore, STM Catania
Research Groups Microelectronics
Thesis type RICERCA
Description The thesis will be done at STM Catania. The goal is to experiment with new industrial tools that use AI and ML to tune constrained random virtual verification sequences, in order to increase coverage.
Required skills The student should have knowledge of:
- Digital electronic design
- Computer architecture
- Object-oriented programming
Deadline 07/03/2025
PROPONI LA TUA CANDIDATURA