TESTGROUP - TESTGROUP
Advanced C++14 Multithreading Modelling of Electronics Systems
Research Groups TESTGROUP - TESTGROUP
Thesis type HARDWARE AND SOFTWARE DESIGN, RESEARCH / EXPERIMENTAL
Application of the advanced multithreading paradigms of C++14 to model the execution of Register-Transfer Level (RTL) components
When designing Electronics Systems, the usage of Register Transfer Level (RTL) languages such as VHDL or Verilog is a compulsory step. One of the big blocking point is the necessity of expressing the concurrent behavior of the components and their interaction in terms of both data and control flow. Concurrency is expressed as dependencies on the value of “signals” shared between “processes”. This peculiarity is especially problematic in two key fields: Verification and High-Level Synthesis (HLS).
For verification purposes, it is extremely difficult and time-consuming to model the concurrent interactions of RTL components and guarantee their correctness. Similarly, HLS struggles in extracting parallelism for high-level programs written in languages such as C/C++ and translate them in RTL, which uses completely different semantics.
In this context, C++14 introduced several novelties to handle concurrency. Most notably, it is possible to natively define asynchronous execution and data-based synchronization points using the “future” construct. These new semantics are interestingly similar to RTL.
The aim of this internship is to perform an in-depth analysis of C++14 “futures” and propose their application to model RTL components, either in terms of Verification or HLD depending on the applicant’s preferences.
Learned Outcomes: Advanced Multithreading, RTL Verification, HLS
Required skills C++ programming, Parallel Programming, VHDL or Verilog
Notes This Thesis is a collaboration with Grenoble Institute of Technology (Grenoble-INP), France
Deadline 29/01/2022 PROPONI LA TUA CANDIDATURA