VLSILAB (VLSI theory, design and applications)
Thesis at STMicroelectronics, Milan: "Power Consumption Estimation in Early Digital Design Stages for MEMS Motion Sensors"
Tesi esterna in azienda
Riferimenti MARIO ROBERTO CASU
Riferimenti esterni Alessandro DE LAURENZIS (STMicroelectronics)
Gruppi di ricerca VLSILAB (VLSI theory, design and applications)
Descrizione The aim of this thesis is the study of average power consumption estimation techniques in early design stages for MEMS sensors and the comparison of the obtained results with those coming from sign-off simulations. The candidate will be involved in multiple steps of physical implementation, including logic synthesis, functional simulation and static timing analysis, using various CAD suites and closely interacting with vendor support resident teams, in order to identify any possible improvements to the tool settings.
The activity will be carried out at AMG (Analog and MEMS Group), MSD (MEMS Sensors Division), STMicroelectronics, Cornaredo Design Center.
CMOS technology downscaling led to a significant increase in the amount of digital logic present in electronic devices. This made them more and more attractive by introducing a growing number of integrated functions, but at the same time has considerably increased chip complexity. Aggressive time to market requires accurate estimation of circuit performances (both timing and power) since the very early design flow steps. For these reasons synergy between designers (responsible of RTL code writing) and implementation engineers (which realize the physical circuits) is a key to get competitive products.
The candidate must be able to analyze the overall architecture of digital integrated devices and have a solid knowledge of physical effects related to power consumption in CMOS circuits; a hand-on experience with HDL (Verilog, VHDL) and scripting languages (preferably TCL) will be a plus. The dissertation will be evaluated in terms of effectiveness, efficiency and portability, with the goal of incorporating final results in the methodologies used for mainstream design flows.
During the thesis the candidate will learn:
- how the digital part of a MEMS sensor is structured;
- which are the key contributors to power consumption and the main low-power digital design techniques;
- how logic synthesis and verification tools are used within the digital implementation methodologies and how to adapt their setup to specific needs.
An expense repayment is foreseen for the entire duration of the thesis.
Conoscenze richieste VHDL or Verilog mandatory. Knowledge of main CAD tools (Synopsys, Cadence). TCL scripting is a plus
Note An average mark of at least 27/30 is required.
Scadenza validita proposta 13/12/2020 PROPONI LA TUA CANDIDATURA