Tesi al Politecnico
Low-energy Razor circuit implementation on FPGA
Parole chiave FPGA, LOW POWER, RAZOR ARCHITECTURE
Riferimenti LUCIANO LAVAGNO
Gruppi di ricerca Microelectronics
Tipo tesi RESEARCH
Descrizione The Razor architecture enables faster (or lower voltage) clocking of a digital circuit by sampling each combinational logic twice, once with a fast clock, and once with a slow clock, detecting differences between the two and recovering from errors.
However, it is plagued by hold violations that must be solved using lock-up latches.
The goal of the thesis is to use a novel technique for lock-up latch optimization that was recently developed in our group, to implement a Razor circuit on an FPGA, to reduce power consumption and/or improve performance.
Conoscenze richieste Digital design, FPGA implementation
Note Skills required: Digital design, FPGA implementation
Expertise acquired: power and performance optimization via safe oversampling
Scadenza validita proposta 08/06/2023 PROPONI LA TUA CANDIDATURA